High-level synthesis, cryptography, and side-channel countermeasures: A comprehensive evaluation

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F21%3A00350674" target="_blank" >RIV/68407700:21240/21:00350674 - isvavai.cz</a>

Výsledek na webu

<a href="https://doi.org/10.1016/j.micpro.2021.104311" target="_blank" >https://doi.org/10.1016/j.micpro.2021.104311</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1016/j.micpro.2021.104311" target="_blank" >10.1016/j.micpro.2021.104311</a>

Jazyk výsledku

angličtina

Název v původním jazyce

High-level synthesis, cryptography, and side-channel countermeasures: A comprehensive evaluation

Popis výsledku v původním jazyce

Side-channel attacks pose a severe threat to both software and hardware cryptographic implementations. Current literature presents various countermeasures against these kinds of attacks, based on approaches such as hiding or masking, implemented either in software, or on register-transfer level or gate level in hardware. However, emerging trends in hardware design lean towards a system-level approach, allowing for faster, less error-prone, design process, an efficient hardware/software co-design, or sophisticated validation, verification, and (co)simulation strategies. In this paper, we propose a Boolean masking scheme suitable for high-level synthesis of substitution-permutation network-based encryption. We implement both unprotected and protected PRESENT, AES/Rijndael and Serpent encryption in C language, utilizing the concept of dynamic logic reconfiguration, synthesize it for Xilinx FPGA, and we compare our results regarding time and area utilization. We evaluate the effectiveness of proposed countermeasures using both specific and non-specific t-test leakage assessment methodology. We discuss the leakage assessment results, and we identify and discuss the related limitations of the system-level approach and the high-level synthesis.

Název v anglickém jazyce

High-level synthesis, cryptography, and side-channel countermeasures: A comprehensive evaluation

Popis výsledku anglicky

Side-channel attacks pose a severe threat to both software and hardware cryptographic implementations. Current literature presents various countermeasures against these kinds of attacks, based on approaches such as hiding or masking, implemented either in software, or on register-transfer level or gate level in hardware. However, emerging trends in hardware design lean towards a system-level approach, allowing for faster, less error-prone, design process, an efficient hardware/software co-design, or sophisticated validation, verification, and (co)simulation strategies. In this paper, we propose a Boolean masking scheme suitable for high-level synthesis of substitution-permutation network-based encryption. We implement both unprotected and protected PRESENT, AES/Rijndael and Serpent encryption in C language, utilizing the concept of dynamic logic reconfiguration, synthesize it for Xilinx FPGA, and we compare our results regarding time and area utilization. We evaluate the effectiveness of proposed countermeasures using both specific and non-specific t-test leakage assessment methodology. We discuss the leakage assessment results, and we identify and discuss the related limitations of the system-level approach and the high-level synthesis.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

—

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2021

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Microprocessors and Microsystems

ISSN

0141-9331

e-ISSN

1872-9436

Svazek periodika

85

Číslo periodika v rámci svazku

104311

Stát vydavatele periodika

NL - Nizozemsko

Počet stran výsledku

13

Strana od-do

1-13

Kód UT WoS článku

000689666100006

EID výsledku v databázi Scopus

2-s2.0-85111677981