Enhancing Quality and Security of the PLL-TRNG

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F23%3A00383035" target="_blank" >RIV/68407700:21240/23:00383035 - isvavai.cz</a>

Výsledek na webu

<a href="https://doi.org/10.46586/tches.v2023.i4.211-237" target="_blank" >https://doi.org/10.46586/tches.v2023.i4.211-237</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.46586/tches.v2023.i4.211-237" target="_blank" >10.46586/tches.v2023.i4.211-237</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Enhancing Quality and Security of the PLL-TRNG

Popis výsledku v původním jazyce

Field Programmable Gate Arrays (FPGAs) are used more and more frequently to implement cryptographic systems, which need random number generators (RNGs) to be embedded in the same device. The main challenge related to the implementation of a generator running inside FPGAs is that the physical source of randomness, such as jittered clock generator, is implemented in the configurable logic area, i.e. in the close vicinity of noisy running algorithms, which can have significant impact on generated numbers or even serve to attack the generator. A possible approach to prevent such influence is the use of Phase-Lock Loops (PLLs), which are separated from the re-configurable logic area inside the FPGA chip. In this paper, we propose a new architecture of the PLL-based TRNG including a method to avoid correlation in the output through control of timing in the sampling process, as well as new embedded tests based on the enhanced stochastic model. We also propose a workflow to help find the best parameters, such as output bitrate and entropy rate. We show that bitrates of around 400 kb/s or more can be achieved, while guaranteeing min-entropy rates per bit higher than 0.98 as required by the latest security standards. 2023, Ruhr-University of Bochum. All rights reserved.

Název v anglickém jazyce

Enhancing Quality and Security of the PLL-TRNG

Popis výsledku anglicky

Field Programmable Gate Arrays (FPGAs) are used more and more frequently to implement cryptographic systems, which need random number generators (RNGs) to be embedded in the same device. The main challenge related to the implementation of a generator running inside FPGAs is that the physical source of randomness, such as jittered clock generator, is implemented in the configurable logic area, i.e. in the close vicinity of noisy running algorithms, which can have significant impact on generated numbers or even serve to attack the generator. A possible approach to prevent such influence is the use of Phase-Lock Loops (PLLs), which are separated from the re-configurable logic area inside the FPGA chip. In this paper, we propose a new architecture of the PLL-based TRNG including a method to avoid correlation in the output through control of timing in the sampling process, as well as new embedded tests based on the enhanced stochastic model. We also propose a workflow to help find the best parameters, such as output bitrate and entropy rate. We show that bitrates of around 400 kb/s or more can be achieved, while guaranteeing min-entropy rates per bit higher than 0.98 as required by the latest security standards. 2023, Ruhr-University of Bochum. All rights reserved.

Druh

J_SC - Článek v periodiku v databázi SCOPUS

CEP obor

—

OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

—

Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2023

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

IACR Transactions on Cryptographic Hardware and Embedded Systems

ISSN

2569-2925

e-ISSN

2569-2925

Svazek periodika

2023

Číslo periodika v rámci svazku

4

Stát vydavatele periodika

DE - Spolková republika Německo

Počet stran výsledku

27

Strana od-do

211-237

Kód UT WoS článku

—

EID výsledku v databázi Scopus

2-s2.0-85170261576