Structural bias in synthesis of sparsely-specified functions

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F24%3A00380769" target="_blank" >RIV/68407700:21240/24:00380769 - isvavai.cz</a>

Výsledek na webu

<a href="https://doi.org/10.1515/itit-2024-0071" target="_blank" >https://doi.org/10.1515/itit-2024-0071</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1515/itit-2024-0071" target="_blank" >10.1515/itit-2024-0071</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Structural bias in synthesis of sparsely-specified functions

Popis výsledku v původním jazyce

Two-level logic minimization is a well-established process that efficiently minimizes functions described in the Sum-of-Products (SOP) form. Current two-level SOP minimizes, like Espresso and Boom, produce optimum or near-optimum results regarding the SOP size. However, in this article we show that an SOP minimization conducted in the standard, multi-output way, significantly worsens the result of the subsequent multi-level synthesis, especially for sparsely-specified functions, regardless of the optimization process and the tool used. In conclusion, we propose using a single-output two-level SOP minimization for sparsely specified functions. In this way, the obtained circuits are sometimes multiple times smaller, while no significant deterioration has been observed for any other functions.

Název v anglickém jazyce

Structural bias in synthesis of sparsely-specified functions

Popis výsledku anglicky

Two-level logic minimization is a well-established process that efficiently minimizes functions described in the Sum-of-Products (SOP) form. Current two-level SOP minimizes, like Espresso and Boom, produce optimum or near-optimum results regarding the SOP size. However, in this article we show that an SOP minimization conducted in the standard, multi-output way, significantly worsens the result of the subsequent multi-level synthesis, especially for sparsely-specified functions, regardless of the optimization process and the tool used. In conclusion, we propose using a single-output two-level SOP minimization for sparsely specified functions. In this way, the obtained circuits are sometimes multiple times smaller, while no significant deterioration has been observed for any other functions.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

—

Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2024

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

it - Information Technology

ISSN

1611-2776

e-ISSN

2196-7032

Svazek periodika

66

Číslo periodika v rámci svazku

4-5

Stát vydavatele periodika

DE - Spolková republika Německo

Počet stran výsledku

11

Strana od-do

103-113

Kód UT WoS článku

001415425400001

EID výsledku v databázi Scopus

2-s2.0-105003439844