Characterisation of analogue MAPS produced in the 65 nm TPSCo process

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21340%2F25%3A00382890" target="_blank" >RIV/68407700:21340/25:00382890 - isvavai.cz</a>

Výsledek na webu

<a href="https://doi.org/10.1088/1748-0221/20/01/C01019" target="_blank" >https://doi.org/10.1088/1748-0221/20/01/C01019</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1088/1748-0221/20/01/C01019" target="_blank" >10.1088/1748-0221/20/01/C01019</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Characterisation of analogue MAPS produced in the 65 nm TPSCo process

Popis výsledku v původním jazyce

Within the context of the ALICE ITS3 collaboration, a set of MAPS small-scale test structures were developed using the 65 nm TPSCo CMOS imaging process with the upgrade of the ALICE inner tracking system as its primary focus. One such sensor, the Circuit Exploratoire 65 nm (CE-65), and its evolution the CE-65v2, were developed to explore charge collection properties for varying configurations including collection layer process (standard, blanket, modified with gap), pixel pitch (15, 18, 22.5 µm), and pixel geometry (square vs hexagonal/staggered). In this work the characterisation of the CE-65v2 chip, based on 55Fe lab measurements and test beams at CERN SPS, is presented. Matrix gain uniformity up to the Script O(5%) level was demonstrated for all considered chip configurations. The CE-65v2 chip achieves a spatial resolution of under 2 µm during beam tests. Process modifications allowing for faster charge collection and less charge sharing result in decreased spatial resolution, but a considerably wider range of operation, with both the 15 µm and 22.5 µm chips achieving over 99% efficiency up to a ~ 180 e- seed threshold. The results serve to validate the 65 nm TPSCo CMOS process, as well as to motivate design choices in future particle detection experiments.

Název v anglickém jazyce

Characterisation of analogue MAPS produced in the 65 nm TPSCo process

Popis výsledku anglicky

Within the context of the ALICE ITS3 collaboration, a set of MAPS small-scale test structures were developed using the 65 nm TPSCo CMOS imaging process with the upgrade of the ALICE inner tracking system as its primary focus. One such sensor, the Circuit Exploratoire 65 nm (CE-65), and its evolution the CE-65v2, were developed to explore charge collection properties for varying configurations including collection layer process (standard, blanket, modified with gap), pixel pitch (15, 18, 22.5 µm), and pixel geometry (square vs hexagonal/staggered). In this work the characterisation of the CE-65v2 chip, based on 55Fe lab measurements and test beams at CERN SPS, is presented. Matrix gain uniformity up to the Script O(5%) level was demonstrated for all considered chip configurations. The CE-65v2 chip achieves a spatial resolution of under 2 µm during beam tests. Process modifications allowing for faster charge collection and less charge sharing result in decreased spatial resolution, but a considerably wider range of operation, with both the 15 µm and 22.5 µm chips achieving over 99% efficiency up to a ~ 180 e- seed threshold. The results serve to validate the 65 nm TPSCo CMOS process, as well as to motivate design choices in future particle detection experiments.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

10303 - Particles and field physics

Projekt

—

Návaznosti

—

Rok uplatnění

2025

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

JOURNAL OF INSTRUMENTATION

ISSN

1748-0221

e-ISSN

—

Svazek periodika

20

Číslo periodika v rámci svazku

1

Stát vydavatele periodika

GB - Spojené království Velké Británie a Severního Irska

Počet stran výsledku

10

Strana od-do

—

Kód UT WoS článku

001439351000001

EID výsledku v databázi Scopus

2-s2.0-85215234854