Low-power sample and hold circuits using current conveyor analogue switches

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21460%2F18%3A00329553" target="_blank" >RIV/68407700:21460/18:00329553 - isvavai.cz</a>

Nalezeny alternativní kódy

RIV/00216305:26220/18:PU126605

Výsledek na webu

<a href="http://dx.doi.org/10.1049/iet-cds.2017.0411" target="_blank" >http://dx.doi.org/10.1049/iet-cds.2017.0411</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1049/iet-cds.2017.0411" target="_blank" >10.1049/iet-cds.2017.0411</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Low-power sample and hold circuits using current conveyor analogue switches

Popis výsledku v původním jazyce

This study presents low-power sample and hold (S/H) circuits using second-generation current conveyor (CCII). Unlike previous S/H circuits, switch of the proposed S/H circuits can be obtained using CCII which works as current conveyor analogue switch (CCAS). The state of CCAS is controlled by sampling pulse that can be applied via its bias current source. The proposed S/H circuits offer low-power consumption, high-speed and absent from non-overlapping clock signal requirements. Three configurations of S/H circuit are proposed, namely single-ended S/H, differential S/H and serial-to-parallel S/H circuits. The proposed S/H circuits have been simulated using 0.18 mu m complementary metal oxide semiconductor (CMOS) process from Taiwan semiconductor manufacturing company (TSMC). The simulation results are used to confirm the workability of the proposed structures.

Název v anglickém jazyce

Low-power sample and hold circuits using current conveyor analogue switches

Popis výsledku anglicky

This study presents low-power sample and hold (S/H) circuits using second-generation current conveyor (CCII). Unlike previous S/H circuits, switch of the proposed S/H circuits can be obtained using CCII which works as current conveyor analogue switch (CCAS). The state of CCAS is controlled by sampling pulse that can be applied via its bias current source. The proposed S/H circuits offer low-power consumption, high-speed and absent from non-overlapping clock signal requirements. Three configurations of S/H circuit are proposed, namely single-ended S/H, differential S/H and serial-to-parallel S/H circuits. The proposed S/H circuits have been simulated using 0.18 mu m complementary metal oxide semiconductor (CMOS) process from Taiwan semiconductor manufacturing company (TSMC). The simulation results are used to confirm the workability of the proposed structures.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

<a href="/cs/project/LO1401" target="_blank" >LO1401: Interdisciplinární výzkum bezdrátových technologií</a><br>

Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2018

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

IET Circuits, Devices & Systems

ISSN

1751-858X

e-ISSN

1751-8598

Svazek periodika

12

Číslo periodika v rámci svazku

4

Stát vydavatele periodika

GB - Spojené království Velké Británie a Severního Irska

Počet stran výsledku

6

Strana od-do

397-402

Kód UT WoS článku

000440944500012

EID výsledku v databázi Scopus

2-s2.0-85051275151