Design and Implementation of a 0.3-V Differential Difference Amplifier

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21460%2F19%3A00340701" target="_blank" >RIV/68407700:21460/19:00340701 - isvavai.cz</a>

Nalezeny alternativní kódy

RIV/00216305:26220/19:PU128368

Výsledek na webu

<a href="https://doi.org/10.1109/TCSI.2018.2866179" target="_blank" >https://doi.org/10.1109/TCSI.2018.2866179</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/TCSI.2018.2866179" target="_blank" >10.1109/TCSI.2018.2866179</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Design and Implementation of a 0.3-V Differential Difference Amplifier

Popis výsledku v původním jazyce

A new silicon realization of an ultra-low-voltage and ultra-low-power differential-difference amplifier (DDA) is presented in this paper. The circuit combines the idea of non-tailed bulk-driven differential pairs with a partial positive feedback used for voltage gain boasting. The DDA operates from V-DD ranging from 0.3 to 0.5 V. For a 0.3-V version, the circuit provides measured DC voltage gain larger than 60 dB, the GBW product of 1.85 kHz, PSRR of 57 dB and the average slew-rate of 1.55 V/ms at 20 pF load capacitance, while consuming only 22 nW of power. An instrumentation amplifier based on the proposed DDA showed the THD of 0.5 % for V-in = 50 mV(pp), and the 3-dB bandwidth of 750 Hz with the voltage gain of 2 V/V. The circuit has been fabricated in a standard n-well 0.18 mu m CMOS process from TSMC. Chip test results agree with simulations. A special design procedure has also been developed that allows the circuit to be optimized under such extreme supply conditions.

Název v anglickém jazyce

Design and Implementation of a 0.3-V Differential Difference Amplifier

Popis výsledku anglicky

A new silicon realization of an ultra-low-voltage and ultra-low-power differential-difference amplifier (DDA) is presented in this paper. The circuit combines the idea of non-tailed bulk-driven differential pairs with a partial positive feedback used for voltage gain boasting. The DDA operates from V-DD ranging from 0.3 to 0.5 V. For a 0.3-V version, the circuit provides measured DC voltage gain larger than 60 dB, the GBW product of 1.85 kHz, PSRR of 57 dB and the average slew-rate of 1.55 V/ms at 20 pF load capacitance, while consuming only 22 nW of power. An instrumentation amplifier based on the proposed DDA showed the THD of 0.5 % for V-in = 50 mV(pp), and the 3-dB bandwidth of 750 Hz with the voltage gain of 2 V/V. The circuit has been fabricated in a standard n-well 0.18 mu m CMOS process from TSMC. Chip test results agree with simulations. A special design procedure has also been developed that allows the circuit to be optimized under such extreme supply conditions.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

—

Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2019

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

IEEE Transactions on Circuits and Systems I: Regular Papers

ISSN

1549-8328

e-ISSN

1558-0806

Svazek periodika

66

Číslo periodika v rámci svazku

2

Stát vydavatele periodika

US - Spojené státy americké

Počet stran výsledku

11

Strana od-do

513-523

Kód UT WoS článku

000457357200006

EID výsledku v databázi Scopus

2-s2.0-85053104450