A compact power-efficient 0.5 V fully differential difference amplifier

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21460%2F19%3A00340708" target="_blank" >RIV/68407700:21460/19:00340708 - isvavai.cz</a>

Nalezeny alternativní kódy

RIV/00216305:26220/19:PU131713

Výsledek na webu

<a href="https://doi.org/10.1016/j.aeue.2019.04.007" target="_blank" >https://doi.org/10.1016/j.aeue.2019.04.007</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1016/j.aeue.2019.04.007" target="_blank" >10.1016/j.aeue.2019.04.007</a>

Jazyk výsledku

angličtina

Název v původním jazyce

A compact power-efficient 0.5 V fully differential difference amplifier

Popis výsledku v původním jazyce

This brief presents a novel compact CMOS Fully Differential Difference Amplifier (FDDA) structure suitable for extremely low-voltage low-power applications. Unlike the conventional FB-DDAs that employ two differential pairs, the proposed structure employs one differential pair of multiple-input bulk driven MOS transistor (MI-BD MOST) that results in reduced count of current branches and, consequently, of power consumption. The proposed FDDA has the simplest CMOS structure presented in the literature so far. Furthermore, while the voltage supply is 0.5 V and the power consumption is 246.6 nW the circuit enjoys rail-to-rail input common mode range (ICMR), high common mode rejection ratio (CMRR) of 100.3 dB @ DC, power supply rejection ratio (PSRR) of 127.8 dB@ DC, voltage gain of 61.4 dB and gain bandwidth product of 6.98 kHz for 30 pF capacitive load. The total harmonic distortion (THD) is less than 0.08% for 500 mV/1 kHz input sine wave signal. The circuit was designed and simulated in Cadence/Spectre environment using 0.18 mu m CMOS process from TSMC. (C) 2019 Elsevier GmbH. All rights reserved.

Název v anglickém jazyce

A compact power-efficient 0.5 V fully differential difference amplifier

Popis výsledku anglicky

This brief presents a novel compact CMOS Fully Differential Difference Amplifier (FDDA) structure suitable for extremely low-voltage low-power applications. Unlike the conventional FB-DDAs that employ two differential pairs, the proposed structure employs one differential pair of multiple-input bulk driven MOS transistor (MI-BD MOST) that results in reduced count of current branches and, consequently, of power consumption. The proposed FDDA has the simplest CMOS structure presented in the literature so far. Furthermore, while the voltage supply is 0.5 V and the power consumption is 246.6 nW the circuit enjoys rail-to-rail input common mode range (ICMR), high common mode rejection ratio (CMRR) of 100.3 dB @ DC, power supply rejection ratio (PSRR) of 127.8 dB@ DC, voltage gain of 61.4 dB and gain bandwidth product of 6.98 kHz for 30 pF capacitive load. The total harmonic distortion (THD) is less than 0.08% for 500 mV/1 kHz input sine wave signal. The circuit was designed and simulated in Cadence/Spectre environment using 0.18 mu m CMOS process from TSMC. (C) 2019 Elsevier GmbH. All rights reserved.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

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OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

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Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2019

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

AEU-International Journal of Electronics and Communications

ISSN

1434-8411

e-ISSN

1618-0399

Svazek periodika

105

Číslo periodika v rámci svazku

2019

Stát vydavatele periodika

DE - Spolková republika Německo

Počet stran výsledku

7

Strana od-do

71-77

Kód UT WoS článku

000469308400009

EID výsledku v databázi Scopus

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