Timepix4 chipboard and readout concept

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21670%2F25%3A00384251" target="_blank" >RIV/68407700:21670/25:00384251 - isvavai.cz</a>

Nalezeny alternativní kódy

RIV/49777513:23220/25:43975910

Výsledek na webu

<a href="https://doi.org/10.1088/1748-0221/20/06/C06074" target="_blank" >https://doi.org/10.1088/1748-0221/20/06/C06074</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1088/1748-0221/20/06/C06074" target="_blank" >10.1088/1748-0221/20/06/C06074</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Timepix4 chipboard and readout concept

Popis výsledku v původním jazyce

This paper presents a modular readout and chipboard concept developed for the Timepix4 hybrid pixel detector, a high-performance ASIC featuring 448 x 512 pixels and sub-nanosecond timing resolution. Building on the success of Timepix3, Timepix4 supports both frame-based and data-driven acquisition modes with data rates up to 3.6 MHits/mm2/s and 195 ps time binning. The chip can be integrated via wire-bonding or Through-Silicon-Via (TSV) technology, allowing full four-side tiling for scalable detector arrays. The modular chipboard system, consisting of a detector module and a baseboard, simplifies power delivery and data transmission using a single 12 V supply and Ethernet-style cabling. A commercial FPGA-based readout supports up to four detectors with Gigabit Ethernet and PCIe interfaces. The concept was successfully validated at CERN SPS with heavy-ion beams, demonstrating system stability and high data integrity. Ongoing development focuses on enhanced power and cooling systems, multi-chip integration, and improved software support for advanced experimental setups.

Název v anglickém jazyce

Timepix4 chipboard and readout concept

Popis výsledku anglicky

This paper presents a modular readout and chipboard concept developed for the Timepix4 hybrid pixel detector, a high-performance ASIC featuring 448 x 512 pixels and sub-nanosecond timing resolution. Building on the success of Timepix3, Timepix4 supports both frame-based and data-driven acquisition modes with data rates up to 3.6 MHits/mm2/s and 195 ps time binning. The chip can be integrated via wire-bonding or Through-Silicon-Via (TSV) technology, allowing full four-side tiling for scalable detector arrays. The modular chipboard system, consisting of a detector module and a baseboard, simplifies power delivery and data transmission using a single 12 V supply and Ethernet-style cabling. A commercial FPGA-based readout supports up to four detectors with Gigabit Ethernet and PCIe interfaces. The concept was successfully validated at CERN SPS with heavy-ion beams, demonstrating system stability and high data integrity. Ongoing development focuses on enhanced power and cooling systems, multi-chip integration, and improved software support for advanced experimental setups.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

20205 - Automation and control systems

Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2025

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Journal of Instrumentation

ISSN

1748-0221

e-ISSN

1748-0221

Svazek periodika

20

Číslo periodika v rámci svazku

6

Stát vydavatele periodika

IT - Italská republika

Počet stran výsledku

9

Strana od-do

1-9

Kód UT WoS článku

001522134000001

EID výsledku v databázi Scopus

2-s2.0-105009800820