Side-Channel and Fault Resistant ASCON Implementation: A Detailed Hardware Evaluation

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F24%3APU154848" target="_blank" >RIV/00216305:26220/24:PU154848 - isvavai.cz</a>
Result on the web
<a href="https://ieeexplore.ieee.org/document/10682712" target="_blank" >https://ieeexplore.ieee.org/document/10682712</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/ISVLSI61997.2024.00063" target="_blank" >10.1109/ISVLSI61997.2024.00063</a>

Result language
angličtina
Original language name
Side-Channel and Fault Resistant ASCON Implementation: A Detailed Hardware Evaluation
Original language description
In this work, we present various hardware implementations for the lightweight cipher ASCON, which was recently selected as the winner of the NIST organized Lightweight Cryptography (LWC) competition. We cover encryption + tag generation and decryption + tag verification for the ASCON hash function and ASCON AEAD. On top of the usual (unprotected) implementation, we present side-channel protection (threshold countermeasure) and triplication/majority-based fault protection. To the best of our knowledge, this is the first protected hardware implementation of ASCON with respect to side-channel and fault inject protection. The side-channel and fault protections work orthogonal to each other (i.e., either one can be turned on/off without affecting the other). We present ASIC and FPGA benchmarks for all our implementations (hash and AEAD) with/without countermeasures for varying input sizes.
Czech name
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Czech description
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Project
<a href="/en/project/VJ02010010" target="_blank" >VJ02010010: Tools for AI-enhanced Security Verification of Cryptographic Devices</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2024
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
ISBN
979-8-3503-5412-6
ISSN
2159-3477
e-ISSN
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Number of pages
6
Pages from-to
307-312
Publisher name
IEEE Computer Society
Place of publication
Knoxville, Tennessee, USA
Event location
Knoxville, Tennessee
Event date
Jul 1, 2024
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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