Simulation and Prototyping Multiprocessor SoC with Hybrid Pipeline/Farm Architecture

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F02%3APU36183" target="_blank" >RIV/00216305:26230/02:PU36183 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Simulation and Prototyping Multiprocessor SoC with Hybrid Pipeline/Farm Architecture
Original language description
Process- and thread-level parallelism is very often exploited in asynchronous processor pipelines for embedded applications, recently on a chip. The paper deals with simulation of pipelines with one or more workers in each pipeline stage. The number of workers can be adjusted to balance execution time of other stages so as to keep efficiency high. Simulation-based prototyping of such pipeline processor farms using Transim tool can account for communication delays, multitasking, data-dependent variationss in workload, CPUs with different speeds, etc. Simulation results for a given task divisible to a few subtasks of arbitrary duration are presented as well as a particular example of a power of a matrix.
Czech name
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Czech description
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Project
<a href="/en/project/GA102%2F02%2F0503" target="_blank" >GA102/02/0503: Parallel performance prediction and tuning</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2002
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of IEEE Design and Diagnostics of Electronic Circuits and System Workshop
ISBN
80-214-2094-4
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
296-299
Publisher name
Faculty of Information Technology BUT
Place of publication
Brno
Event location
Brno
Event date
Apr 17, 2002
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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