Packet Classification Algorithms
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F11%3APU96079" target="_blank" >RIV/00216305:26230/11:PU96079 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Packet Classification Algorithms
Original language description
As network speeds are increasing, the demand for hardware acceleration of packet classification in FPGAs or ASICs is growing. Nowadays algorithms implemented in hardware can achieve multigigabit speeds, but they suffer with great memory overhead. This paper presents three packet classification algorithms with strong potential for acceleration in ASIC or FPGA, while the memory requirements are kept reasonably low.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
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Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2011
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Počítačové architektury a diagnostika
ISBN
978-80-227-3552-0
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
157-162
Publisher name
Faculty of Electrical Engineering and Information Technology, Slovak University of Technology in Bratislava
Place of publication
Stará Lesná
Event location
Stará Lesná
Event date
Sep 12, 2011
Type of event by nationality
CST - Celostátní akce
UT code for WoS article
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