Compact Library of Efficient Polymorphic Gates based on Ambipolar Transistors

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F17%3APU123248" target="_blank" >RIV/00216305:26230/17:PU123248 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/DTIS.2017.7930180" target="_blank" >http://dx.doi.org/10.1109/DTIS.2017.7930180</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DTIS.2017.7930180" target="_blank" >10.1109/DTIS.2017.7930180</a>

Result language
angličtina
Original language name
Compact Library of Efficient Polymorphic Gates based on Ambipolar Transistors
Original language description
Main goal of this paper is to propose a compact library of polymorphic gates based on suitable type of reconfigurable transistors. In fact, their exploitation brings a significant advantage for space-efficient synthesis of complex polymorphic circuits. Actual behaviour of those transistors closely depends on so called ambipolar property. That particular aspect simply allows the selection of n- or p- channel operating mode of the transistor structures which is controlled by means of switching the voltage level at a dedicated control electrode. The gates were developed by an evolution approach using Cartesian genetic programming. Various discrete switch-level ambipolar transistor models extended by taking into account the threshold voltage drop degradation effect were used. A diverse range of polymorphic gates were designed, which clearly shows significant transistor savings compared to the conventional approaches. Finally, the individual components that belong to the library also suggest the opportunity how to considerably reduce the target size of complex polymorphic circuits.
Czech name
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Czech description
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2017
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
2017 12th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)
ISBN
978-1-5090-6376-5
ISSN
—
e-ISSN
—
Number of pages
6
Pages from-to
155-160
Publisher name
IEEE Circuits and Systems Society
Place of publication
Palma de Mallorca
Event location
Palma de Mallorca
Event date
Apr 4, 2017
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000403402000031

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