Triple Modular Redundancy Used in Field Programmable Neural Networks

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F17%3APU127276" target="_blank" >RIV/00216305:26230/17:PU127276 - isvavai.cz</a>
Result on the web
<a href="https://www.fit.vut.cz/research/publication/11446/" target="_blank" >https://www.fit.vut.cz/research/publication/11446/</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/EWDTS.2017.8110128" target="_blank" >10.1109/EWDTS.2017.8110128</a>

Result language
angličtina
Original language name
Triple Modular Redundancy Used in Field Programmable Neural Networks
Original language description
This paper presents the concepts of FPNA and FPNN, used for the approximation of artificial neural networks in FPGAs and discusses the usage of TMR technique in order to reach a fault tolerance. The schemes of the FPGA implementation are presented. The results of experiments determining the FPGA resources utilization with different usage of the TMR technique are provided.
Czech name
—
Czech description
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Project
<a href="/en/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2017
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of IEEE East-West Design & Test Symposium
ISBN
978-1-5386-3299-4
ISSN
—
e-ISSN
—
Number of pages
6
Pages from-to
1-6
Publisher name
IEEE Computer Society
Place of publication
Novi Sad
Event location
Dr Zorana Đinđića 1, 21101, Novi Sad
Event date
Sep 29, 2017
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000426878200101

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