Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-based Experimental Robot Controller

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F18%3APU130722" target="_blank" >RIV/00216305:26230/18:PU130722 - isvavai.cz</a>

Result on the web

<a href="https://www.fit.vut.cz/research/publication/11705/" target="_blank" >https://www.fit.vut.cz/research/publication/11705/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DSD.2018.00051" target="_blank" >10.1109/DSD.2018.00051</a>

Result language

angličtina

Original language name

Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-based Experimental Robot Controller

Original language description

Various electronic systems play an important role in our everyday lives. Some of them serve for fun or to make our lives easier. These systems are useful but not necessary; when they malfunction, the consequences are not critical. On the other hand, there are systems which are more or less critical, and their failure can cause undesirable consequences. For example, a failure in medicine, aviation, the army or automotive systems can cause high economic losses and/or endanger human health. These systems must be protected against the impact of faults, and flawless operation must be ensured. Fault tolerance is one of the techniques that will ensure this. There are many fault-tolerance methodologies targeted towards various systems and technologies, and new methodologies are being investigated. It is also important to verify these techniques; this is the main topic of this paper. An evaluation platform for testing fault-tolerance methodologies targeted towards SRAM-based FPGAs (Field Programmable Gate Arrays) is presented and demonstrated. A robot for seeking a path through a maze and the processor-based robot controller serve as an experimental system case study. Experimental results with the unhardened and hardened versions of the processor-based robot controller are presented and discussed.

Czech name

—

Czech description

—

Type

D - Article in proceedings

CEP classification

—

OECD FORD branch

20206 - Computer hardware and architecture

Project

<a href="/en/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Publication year

2018

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Proceedings of the 2018 21st Euromicro Conference on Digital System Design

ISBN

978-1-5386-7376-8

ISSN

—

e-ISSN

—

Number of pages

8

Pages from-to

229-236

Publisher name

IEEE Computer Society

Place of publication

Praha

Event location

FIT ČVUT, Thákurova 9, 160 00 Praha 6

Event date

Aug 29, 2018

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

000537466600035