Regular Expression Matching with Pipelined Delayed Input DFAs for High-speed Networks
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F18%3APU130728" target="_blank" >RIV/00216305:26230/18:PU130728 - isvavai.cz</a>
Result on the web
<a href="https://www.fit.vut.cz/research/publication/11711/" target="_blank" >https://www.fit.vut.cz/research/publication/11711/</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1145/3230718.3230730" target="_blank" >10.1145/3230718.3230730</a>
Alternative languages
Result language
angličtina
Original language name
Regular Expression Matching with Pipelined Delayed Input DFAs for High-speed Networks
Original language description
Regular expression matching (RE matching) is a widely used operation in network security monitoring applications. With the speed of network links increasing to 100 Gbps and 400 Gbps, it is necessary to speed up packet processing and provide RE matching at such high speeds. Although many RE matching algorithms and architectures have been designed, none of them supports 100 Gbps throughput together with fast updates of an RE set. Therefore, this paper focuses on the design of a new hardware architecture that addresses both these requirements. The proposed architecture uses multiple highly memory-efficient Delayed Input DFAs (D2FAs), which are organized to a processing pipeline. As all D2FAs in the pipeline have only local communication, the proposed architecture is able to operate at high frequency even for a large number of parallel engines, which allows scaling throughput to hundreds of gigabits per second. The paper also analyses how to scale the number of engines and the capacity of buffers to achieve desired throughput. Using the parameters obtained while matching two sets of REs (represented by D2FAs) in a real network traffic, the architecture can be tuned for wire-speed throughput of 400 Gbps.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
20206 - Computer hardware and architecture
Result continuities
Project
<a href="/en/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2018
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
ANCS 2018 - Proceedings of the 2018 Symposium on Architectures for Networking and Communications Systems
ISBN
978-1-4503-5902-3
ISSN
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e-ISSN
—
Number of pages
7
Pages from-to
104-110
Publisher name
Association for Computing Machinery
Place of publication
Ithaca, NY
Event location
Ithaca, NY
Event date
Jul 23, 2018
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000474465600010