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High-speed Regular Expression Matching with Pipelined Automata

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F16%3A10130777" target="_blank" >RIV/63839172:_____/16:10130777 - isvavai.cz</a>

  • Alternative codes found

    RIV/00216305:26230/16:PU122836

  • Result on the web

  • DOI - Digital Object Identifier

Alternative languages

  • Result language

    angličtina

  • Original language name

    High-speed Regular Expression Matching with Pipelined Automata

  • Original language description

    Pattern matching is a complex task which is widely used in network security monitoring applications. With the growing speed of network links, pattern matching architectures have to be improved in order to retain wire-speed processing. Multi-striding is a well-known technique on how to increase throughput of pattern matching architectures. In the paper we provide an analysis of scalability of multi-striding and show that it does not scale well and cannot be used for 100Gbps throughput because utilization of FPGA resources grows exponentially. Therefore, we have designed a new hardware architecture for high-speed pattern matching that combines the multi-striding technique and parallel processing using pipelined finite state machines (FSMs). The architecture shares a single packet buffer for all parallel FSMs. Efficient implementation of the packet buffer reduces the number of BlockRAMs to 18% when compared to simple parallel implementation. Instead of multiplexing input data, the architecture pipelines the states of FSMs. Such pipelined processing with only local communication has a direct positive impact on frequency and throughput and allows us to scale the architecture to hundreds of Gbps.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    IN - Informatics

  • OECD FORD branch

Result continuities

  • Project

    <a href="/en/project/LM2015042" target="_blank" >LM2015042: E-infrastructure CESNET</a><br>

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Others

  • Publication year

    2016

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proceedings of the 2016 International Conference on Field Programmable Technology

  • ISBN

    978-1-5090-5602-6

  • ISSN

  • e-ISSN

  • Number of pages

    8

  • Pages from-to

    93-100

  • Publisher name

    IEEE Computer Society

  • Place of publication

    Xi'an, China

  • Event location

    Xi'an, China

  • Event date

    Dec 7, 2016

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article