All

What are you looking for?

All
Projects
Results
Organizations

Quick search

  • Projects supported by TA ČR
  • Excellent projects
  • Projects with the highest public support
  • Current projects

Smart search

  • That is how I find a specific +word
  • That is how I leave the -word out of the results
  • “That is how I can find the whole phrase”

Late Breaking Result: FPGA-Based Emulation and Fault Injection for CNN Inference Accelerators

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F26%3A0193424" target="_blank" >RIV/00216305:26230/26:0193424 - isvavai.cz</a>

  • Result on the web

    <a href="http://dx.doi.org/10.23919/DATE64628.2025.10992992" target="_blank" >http://dx.doi.org/10.23919/DATE64628.2025.10992992</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.23919/DATE64628.2025.10992992" target="_blank" >10.23919/DATE64628.2025.10992992</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    Late Breaking Result: FPGA-Based Emulation and Fault Injection for CNN Inference Accelerators

  • Original language description

    A new field programmable gate array (FPGA)-based emulation platform is proposed to accelerate fault tolerance analysis of inference accelerators of convolutional neural networks (CNN). For a given CNN model, hardware accelerator architecture, and FT analysis target, an FPGA-based CNN implementation is generated (with the help of the Tengine framework), and fault injection logic is added. In our first case study, we report how the classification accuracy drop depends on the faults injected into multipliers used in Multiply-and-Accumulate Units of NVDLA inference accelerator executing ResNet-18 CNN. The FT analysis emulated on Zynq UltraScale+ SoC is an order of magnitude faster than software emulation.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

  • OECD FORD branch

    10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Result continuities

  • Project

    <a href="/en/project/GA24-10990S" target="_blank" >GA24-10990S: Hardware-Aware Machine Learning: From Automated Design to Innovative and Explainable Solutions</a><br>

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Others

  • Publication year

    2025

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    2025 Design, Automation & Test in Europe Conference & Exhibition (DATE)

  • ISBN

    978-3-9826741-0-0

  • ISSN

  • e-ISSN

  • Number of pages

    2

  • Pages from-to

    1-2

  • Publisher name

    Institute of Electrical and Electronics Engineers

  • Place of publication

    Lyon

  • Event location

    Lyon

  • Event date

    Mar 31, 2025

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article

    001506972600215