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On measurement of impact of the metallization and FPGA design to the changes of slice parameters and generation of delay faults (Stability of timing parameters of 45nm FPGA Spartan 6)

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F46747885%3A24220%2F12%3A%230002015" target="_blank" >RIV/46747885:24220/12:#0002015 - isvavai.cz</a>

  • Result on the web

    <a href="http://www.scopus.com" target="_blank" >http://www.scopus.com</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1109/FPL.2012.6339167" target="_blank" >10.1109/FPL.2012.6339167</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    On measurement of impact of the metallization and FPGA design to the changes of slice parameters and generation of delay faults (Stability of timing parameters of 45nm FPGA Spartan 6)

  • Original language description

    The rapidly growing world of FPGA devices offers important as well as interesting platforms for analyses of process scaling. It creates also new study opportunities in case of new process variations and degradation effects. Changes in parameters of FPGAsin time or under either power supply voltage or temperature variations result in timing variations or delays and may affect the final design quality and dependability. Such timing variations may result in delay faults, up to the final device or equipment malfunction or failure. FPGA designs must be carefully tested and simulated during the design phase. This area is well-covered by many papers and publications and being investigated again with the new processes coming every approximately 2 years. Thispaper investigates the area of effects caused by the FPGA chip design and metallization or design trade-offs. The paper presents interesting results obtained during various tests including the important values of the total delays caused b

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    JC - Computer hardware and software

  • OECD FORD branch

Result continuities

  • Project

  • Continuities

    S - Specificky vyzkum na vysokych skolach

Others

  • Publication year

    2012

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012

  • ISBN

    978-1-4673-2257-7

  • ISSN

  • e-ISSN

  • Number of pages

    4

  • Pages from-to

    743-746

  • Publisher name

  • Place of publication

  • Event location

    Oslo

  • Event date

    Aug 29, 2012

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article