On reliability enhancement using adaptive core voltage scaling and variations on nanoscale FPGAs
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F46747885%3A24220%2F14%3A%230003129" target="_blank" >RIV/46747885:24220/14:#0003129 - isvavai.cz</a>
Result on the web
<a href="http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6841917&queryText%3DOn+reliability+enhancement+using+adaptive+core+voltage+scaling+and+variations+on+nanoscale+FPGAs" target="_blank" >http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6841917&queryText%3DOn+reliability+enhancement+using+adaptive+core+voltage+scaling+and+variations+on+nanoscale+FPGAs</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/LATW.2014.6841917" target="_blank" >10.1109/LATW.2014.6841917</a>
Alternative languages
Result language
angličtina
Original language name
On reliability enhancement using adaptive core voltage scaling and variations on nanoscale FPGAs
Original language description
Rapidly growing portfolio of new technologies in design and manufacturing of advanced integrated circuits allow higher integration of complex structures in ultra-high nano-scale densities. However, the real new devices are sensitive subjects to unacceptable effects of changes of the internal nanostructures. Changes in parameters due to process variations or device aging along the working or its life-time can result in significant in large timing variations or critical BTI-inducted delays and may affectthe final design quality and dependability, may result in delay faults, up to the device or equipment malfunction or failure. Also power supply voltage or temperature variations do typically result in significant changes of timing parameters. The presented and tested circuit, method and approach allows extremely simple control of the core voltage during critical operations or during the device lifetime. This paper include also key results of measurement of selected low-power programmable
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/LD13019" target="_blank" >LD13019: Improvement in Reliability of Nano-scale circuits</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2014
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
15th IEEE Latin-American Test Workshop
ISBN
978-1-4799-4711-9
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
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Publisher name
IEEE Computer Society
Place of publication
Brazil
Event location
Fortaleza
Event date
Jan 1, 2014
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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