Logic Testing with Test-per-Clock Pattern Loading and Improved Diagnostic Abilities
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F46747885%3A24220%2F17%3A00004391" target="_blank" >RIV/46747885:24220/17:00004391 - isvavai.cz</a>
Result on the web
<a href="http://ieeexplore.ieee.org/document/7934586/" target="_blank" >http://ieeexplore.ieee.org/document/7934586/</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DDECS.2017.7934586" target="_blank" >10.1109/DDECS.2017.7934586</a>
Alternative languages
Result language
angličtina
Original language name
Logic Testing with Test-per-Clock Pattern Loading and Improved Diagnostic Abilities
Original language description
This paper describes a test response compaction system that preserves diagnostic information and enables performing a test-per-clock offline testing. The test response compaction system is based on a chain of T flip-flops. The T flip-flop signature chain can preserve the information about the position of the first occurrence of the erroneous test response and the information about the clock cycle when the erroneous test response occurred. This information can be used for diagnostic purposes. The paper discusses the possible benefits and limitations of the proposed test pattern compaction scheme. The influence of multiple errors on detection and localization capability of the compaction system and hardware overhead is discussed in the paper as well.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
20206 - Computer hardware and architecture
Result continuities
Project
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Continuities
I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace
Others
Publication year
2017
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings - 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuit and Systems, DDECS 2017
ISBN
978-153860471-7
ISSN
2334-3133
e-ISSN
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Number of pages
6
Pages from-to
54-59
Publisher name
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Place of publication
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Event location
Dresden
Event date
Jan 1, 2017
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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