Test response compaction method with improved detection and diagnostic abilities

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F46747885%3A24220%2F18%3A00004392" target="_blank" >RIV/46747885:24220/18:00004392 - isvavai.cz</a>

Result on the web

<a href="https://api.elsevier.com/content/article/eid/1-s2.0-S0026271417304924" target="_blank" >https://api.elsevier.com/content/article/eid/1-s2.0-S0026271417304924</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1016/j.microrel.2017.10.016" target="_blank" >10.1016/j.microrel.2017.10.016</a>

Result language

angličtina

Original language name

Test response compaction method with improved detection and diagnostic abilities

Original language description

This paper describes a test response compaction method that preserves diagnostic information and enables performing a test-per-clock offline test. The test response compaction system is based on a chain of T flip-flops. The T flip-flop signature chain can preserve the information about the positions of the erroneous test response occurrence and the information about the clock cycle when the erroneous test responses occurred. This information can be used for diagnostic purposes. An algorithm that localizes errors according to the T flip-flop chain output is presented. The paper discusses the possible benefits and limitations of the proposed test pattern compaction scheme. The influence of multiple errors on detection and localization capability of the compaction system and hardware overhead is discussed in the paper as well. The probability of error masking is analyzed, the proposed scheme provides substantially lower masking probability than a D flip-flop chain and a MISR. The scheme can spare the test time by the test-per-clock arrangement. The hardware overhead and reached test time are given for several benchmark circuits in the paper as well.

Czech name

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Czech description

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Type

J_imp - Article in a specialist periodical, which is included in the Web of Science database

CEP classification

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OECD FORD branch

20206 - Computer hardware and architecture

Project

—

Continuities

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Publication year

2018

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Name of the periodical

Microelectronics Reliability

ISSN

0026-2714

e-ISSN

—

Volume of the periodical

80

Issue of the periodical within the volume

JA

Country of publishing house

NL - THE KINGDOM OF THE NETHERLANDS

Number of pages

8

Pages from-to

249-256

UT code for WoS article

000423891400030

EID of the result in the Scopus database

2-s2.0-85034271519