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Yield and Defect Level Prediction of Designed Printed Circuit Board

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F49777513%3A23220%2F11%3A43914916" target="_blank" >RIV/49777513:23220/11:43914916 - isvavai.cz</a>

  • Result on the web

    <a href="http://dx.doi.org/10.1109/ISSE.2011.6053570" target="_blank" >http://dx.doi.org/10.1109/ISSE.2011.6053570</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1109/ISSE.2011.6053570" target="_blank" >10.1109/ISSE.2011.6053570</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    Yield and Defect Level Prediction of Designed Printed Circuit Board

  • Original language description

    In this paper a new prediction tool is presented, which can provide both yield and defect level predictions. The tool, which is based on DPMO (defects per million opportunities) metric, is intended for newly designed printed circuit board assemblies. Itis programmed in Visual Basic for Application (VBA) and it can be operated in MS Excel environment. Yield prediction is based on so called the yield-DPMO model that is an extension of the yield prediction model, which was created in my dissertation and published in the paper [1]. The yield-DPMO model provides more outputs for quality planners then yield prediction model. The defect level prediction is based on the so called the "defect level-DPMO" model, which works on the basis of complexity based estimate, where from inputs data are determined the defect spectrums and tests coverage. The advantage of DPMO is the fact that it is fully comparable metric and it is not associated only with the certain manufacturing line. Thanks to this to

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    JS - Reliability and quality management, industrial testing

  • OECD FORD branch

Result continuities

  • Project

  • Continuities

    S - Specificky vyzkum na vysokych skolach

Others

  • Publication year

    2011

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    34th International Spring Seminar on Electronics Technology

  • ISBN

    978-1-4577-2112-0

  • ISSN

    2161-2528

  • e-ISSN

  • Number of pages

    6

  • Pages from-to

    162-167

  • Publisher name

    IEEE

  • Place of publication

    Piscataway

  • Event location

    Tatranská Lomnica

  • Event date

    May 11, 2011

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article