Experience in Virtual Testing of RSD Cyclic A/D converters

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F09%3A00157681" target="_blank" >RIV/68407700:21230/09:00157681 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Experience in Virtual Testing of RSD Cyclic A/D converters
Original language description
This paper deals with the ADC non-linearity extraction using a newly developed Virtual Testing Environment (VTE). The VTE proposed is built on Verilog-A implementation of the Servo-Loop unit fully integrated into Cadence design environment. The Servo-Loop method used is aimed at the non-linearity extraction of static ADC transfer curve; in this paper, we prove an advanced Servo-Loop version focusing on behavioral and transistor-level example of the Residual Signed Digit (RSD) cyclic A/D converter design. Powerful capabilities of the proposed VTE were successfully confirmed by a large set of behavioral and transistor-level simulations in Spectre.
Czech name
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Czech description
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Project
<a href="/en/project/GA102%2F07%2F1186" target="_blank" >GA102/07/1186: Sophisticated methods of the analog and mixed-signal circuits design in sub-micron technologies</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2009
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proc. of 12th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2009 (DDECS'09)
ISBN
978-1-4244-3339-1
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
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Publisher name
IEEE Computer Society Press
Place of publication
Los Alamitos
Event location
Liberec
Event date
Apr 15, 2009
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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