SiC graphene FET with polydimethylglutharimide as a gate dielectric layer

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F14%3A00222420" target="_blank" >RIV/68407700:21230/14:00222420 - isvavai.cz</a>

Result on the web

<a href="http://dx.doi.org/10.1109/ASDAM.2014.6998639" target="_blank" >http://dx.doi.org/10.1109/ASDAM.2014.6998639</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/ASDAM.2014.6998639" target="_blank" >10.1109/ASDAM.2014.6998639</a>

Result language

angličtina

Original language name

SiC graphene FET with polydimethylglutharimide as a gate dielectric layer

Original language description

Graphene is perspective material for future carbon based electronics, flexible electronics and other applications. The necessary condition for the commercial use is the high quality graphene growth and semiconductor technology compatible process of whole field effect transistor (FET). One of suitable method for large scale graphene monolayer preparation is the thermal annealing of semi-insulating SiC substrate. One important task of graphene FET process is reliable, cheap and simple gate structure preparation. In this work we present our results of using MicroChem Lift-Off Resist (LOR) layer as a dielectric layer for SiC graphene FETs. LOR resist is based on polydimethylglutharimide. Its unique properties enable to perform exceptionally well resolution imaging, easy process tuning, high yields and superior deposition line width control. In the case of polymer based dielectric layers the breakdown voltage is important parameter. We prepared two sets of different capacitor structures with LOR dielectric layer and Au/Cr electrodes. The first set exhibits very low breakdown voltages (about 3 V). The optimisation of the LOR layer deposition process in the second set increased the breakdown voltage over 40 V keeping the leakage current lower than 2 nA. The second process with LOR layer was used for the preparation of graphene FETs on SiC substrates. The first measurements show resistivity dependence on gate voltage.

Czech name

—

Czech description

—

Type

D - Article in proceedings

CEP classification

—

OECD FORD branch

20201 - Electrical and electronic engineering

Project

<a href="/en/project/GAP108%2F11%2F0894" target="_blank" >GAP108/11/0894: Growth and processing of graphene layers on silicon carbide</a><br>

Continuities

S - Specificky vyzkum na vysokych skolach

Publication year

2014

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

10th International Conference on Advanced Semiconductor Devices and Microsystems ASDAM 2014 Conference Proceedings

ISBN

978-1-4799-5475-9

ISSN

2475-2916

e-ISSN

—

Number of pages

4

Pages from-to

33-36

Publisher name

Slovak University of Technology in Bratislava

Place of publication

Bratislava

Event location

Smolenice

Event date

Oct 20, 2014

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

000412228100008