Reduction of Negative Voltage Spike for SiC based MOSFET Circuit

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F24%3A00375720" target="_blank" >RIV/68407700:21230/24:00375720 - isvavai.cz</a>
Result on the web
<a href="https://poster.fel.cvut.cz/poster2024/" target="_blank" >https://poster.fel.cvut.cz/poster2024/</a>
DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Reduction of Negative Voltage Spike for SiC based MOSFET Circuit
Original language description
In this study, the transil diode and the diode in antiparallel to the gate, which functions as a driver, are used to reduce the negative gate voltage spikes for the SiC based MOSFET half-bridge converter. SiC MOSFETs are capable of operating at high voltages, high frequencies, low on-state resistance, and minimal temperature fluctuations. Because of the high dv/dt of the half-bridge converter, the high-side MOSFET will experience a fast-switching transient that will negatively affect the parasitic components and generate negative voltage spikes on the low-side MOSFET that could damage the switches or overstress the circuit for safe operation. The circuits are simulated at different rise and fall time using the software called SIMPLIS/SIMETRIX.
Czech name
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Czech description
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Publication year
2024
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the International Student Scientific Conference Poster – 28/2024
ISBN
978-80-01-07299-8
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
165-169
Publisher name
Fakulta elektrotechnická
Place of publication
Praha
Event location
Prague
Event date
May 23, 2024
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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