Synthesis of Finite State Machines on Memristor Crossbars

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F18%3A00322412" target="_blank" >RIV/68407700:21240/18:00322412 - isvavai.cz</a>

Result on the web

<a href="http://dx.doi.org/10.1109/DDECS.2018.000-3" target="_blank" >http://dx.doi.org/10.1109/DDECS.2018.000-3</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DDECS.2018.000-3" target="_blank" >10.1109/DDECS.2018.000-3</a>

Result language

angličtina

Original language name

Synthesis of Finite State Machines on Memristor Crossbars

Original language description

Memristor device represents one of the most relevant technologies to deal with CMOS technological issues. In the scientific literature, a relevant amount of works have discussed the memristor device, with a particular emphasis on memristor-based crossbar architectures. However, while the synthesis of combinational logic circuits is widely discussed, the same cannot be said for sequential logic circuits. In this work, we propose a new approach for synthesizing sequential circuits based on memristor crossbar, by enhancing an existing architecture. This approach only exploits memristors within the crossbar for implementing the state feedback mechanism, with the aim of advancing the integration process of memristor-based circuits. Moreover, to provide an automated synthesis process of memristor-based sequential circuits, we extend a pre-existing automated synthesis framework so it can be integrated with widely used tools and formats as register-transfer level (RTL) or Berkeley Logic Interchange Format (BLIF) files. We performed several experiments on publicly available benchmarks in order to compare the proposed architecture against its predecessor in terms of circuit integration and efficiency. Obtained results highlight acceptable overheads (up to a maximum of 24%) compared with the opportunity of integration offered by the proposed architecture.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

—

OECD FORD branch

20206 - Computer hardware and architecture

Project

—

Continuities

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Publication year

2018

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Proc. of 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

ISBN

978-1-5386-5755-3

ISSN

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e-ISSN

2473-2117

Number of pages

6

Pages from-to

107-112

Publisher name

IEEE

Place of publication

Piscataway, NJ

Event location

Budapest

Event date

Apr 25, 2018

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

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