Astute Approach to Handling Memory Layouts of Regular Data Structures

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216208%3A11320%2F22%3A10492531" target="_blank" >RIV/00216208:11320/22:10492531 - isvavai.cz</a>

Výsledek na webu

<a href="https://link.springer.com/chapter/10.1007/978-3-031-22677-9_27" target="_blank" >https://link.springer.com/chapter/10.1007/978-3-031-22677-9_27</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1007/978-3-031-22677-9_27" target="_blank" >10.1007/978-3-031-22677-9_27</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Astute Approach to Handling Memory Layouts of Regular Data Structures

Popis výsledku v původním jazyce

Programmers of high-performance applications face many challenging aspects of contemporary hardware architectures. One of the critical aspects is the efficiency of memory operations which is affected not only by the hardware parameters such as memory throughput or cache latency but also by the data-access patterns, which may influence the utilization of the hardware, such as re-usability of the cached data or coalesced data transactions. Therefore, a performance of an algorithm can be highly impacted by the layout of its data structures or the order of data processing which may translate into a more or less optimal sequence of memory operations. These effects are even more pronounced on highly-parallel platforms, such as GPUs, which often employ specific execution models (lock-step) or memory models (shared memory). In this work, we propose a modern, astute approach for managing and implementing memory layouts with first-class structures that is very efficient and straightforward. This approach was im

Název v anglickém jazyce

Astute Approach to Handling Memory Layouts of Regular Data Structures

Popis výsledku anglicky

Programmers of high-performance applications face many challenging aspects of contemporary hardware architectures. One of the critical aspects is the efficiency of memory operations which is affected not only by the hardware parameters such as memory throughput or cache latency but also by the data-access patterns, which may influence the utilization of the hardware, such as re-usability of the cached data or coalesced data transactions. Therefore, a performance of an algorithm can be highly impacted by the layout of its data structures or the order of data processing which may translate into a more or less optimal sequence of memory operations. These effects are even more pronounced on highly-parallel platforms, such as GPUs, which often employ specific execution models (lock-step) or memory models (shared memory). In this work, we propose a modern, astute approach for managing and implementing memory layouts with first-class structures that is very efficient and straightforward. This approach was im

Druh

D - Stať ve sborníku

CEP obor

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OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

—

Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2022

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

22nd International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2022, Copenhagen, Denmark (Online), 10 - 12 October, 2022

ISBN

978-3-031-22676-2

ISSN

0302-9743

e-ISSN

—

Počet stran výsledku

22

Strana od-do

507-528

Název nakladatele

Springer International Publishing

Místo vydání

Cham, Switzerland

Místo konání akce

København, Denmark

Datum konání akce

10. 10. 2022

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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