Optimization of The DC Motor State Space Controller for FPGA

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26210%2F18%3APU131448" target="_blank" >RIV/00216305:26210/18:PU131448 - isvavai.cz</a>

Výsledek na webu

<a href="https://ieeexplore.ieee.org/document/8624807" target="_blank" >https://ieeexplore.ieee.org/document/8624807</a>

DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Optimization of The DC Motor State Space Controller for FPGA

Popis výsledku v původním jazyce

This paper presents results of continuous development and thesis about the optimization of state space controller for DC motor on FPGA in LabVIEW environment for NI cRIO platform. In the first part, the state space model of the given DC motor is presented in Matlab / Simulink and then the position feedback controller with steady-state error elimination and with state observer with error compensation is designed. After that, it continues with transforming the controller to LabVIEW environment where the code is prepared for FPGA use. Next phase is focused on FPGA hardware resources consumption optimization leads to careful work with fixed-point data type. After successful code compilation on target hardware, the real given DC motor was connected and the series of tests were performed. The output of the thesis is working state space controller running on FPGA and the graphical user interface on real-time host cRIO, which enables the user to control the plant and save the data to the disk.

Název v anglickém jazyce

Optimization of The DC Motor State Space Controller for FPGA

Popis výsledku anglicky

This paper presents results of continuous development and thesis about the optimization of state space controller for DC motor on FPGA in LabVIEW environment for NI cRIO platform. In the first part, the state space model of the given DC motor is presented in Matlab / Simulink and then the position feedback controller with steady-state error elimination and with state observer with error compensation is designed. After that, it continues with transforming the controller to LabVIEW environment where the code is prepared for FPGA use. Next phase is focused on FPGA hardware resources consumption optimization leads to careful work with fixed-point data type. After successful code compilation on target hardware, the real given DC motor was connected and the series of tests were performed. The output of the thesis is working state space controller running on FPGA and the graphical user interface on real-time host cRIO, which enables the user to control the plant and save the data to the disk.

Druh

D - Stať ve sborníku

CEP obor

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OECD FORD obor

20302 - Applied mechanics

Projekt

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Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2018

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the 2018 18th International Conference on Mechatronics – Mechatronika (ME)

ISBN

978-80-214-5543-6

ISSN

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e-ISSN

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Počet stran výsledku

7

Strana od-do

547-553

Název nakladatele

Brno University of Technolgy, 2018

Místo vydání

Brno

Místo konání akce

Brno

Datum konání akce

5. 12. 2018

Typ akce podle státní příslušnosti

CST - Celostátní akce

Kód UT WoS článku

000465104200088