Capacitance Multiplier Using Small Values of Multiplication Factors for Adjustability Extension and Parasitic Resistance Cancellation Technique

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F20%3APU137132" target="_blank" >RIV/00216305:26220/20:PU137132 - isvavai.cz</a>

Výsledek na webu

<a href="https://ieeexplore.ieee.org/document/9159558" target="_blank" >https://ieeexplore.ieee.org/document/9159558</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/ACCESS.2020.3014388" target="_blank" >10.1109/ACCESS.2020.3014388</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Capacitance Multiplier Using Small Values of Multiplication Factors for Adjustability Extension and Parasitic Resistance Cancellation Technique

Popis výsledku v původním jazyce

This paper presents a new concept of a capacitance multiplier using the topology of differential voltage buffer and current conveyor, where the capacitor is connected to the current input terminal. The presented topology overcomes the typical issue known from similar solutions, i.e. creation of an undesired lossy character of the impedance plot. The added feedback path in the structure serves for minimization of the serial parasitic resistance of the current input terminal as well as the output resistance of differential voltage buffer. The electronic driving of the current and voltage internal gains of the active elements allows the adjustment of the capacitance multiplication factor as well as readjustment of the overall capacitance structure between the lossy and lossless modes of operation. The adjustment of the multiplication factor intentionally targets low ranges of gains. Despite that the multiplication factor equals or is less than 1, the range of adjustability is very wide. Simple modifications of the proposed concept leading to the differential-mode operation and enhancement of the multiplication factor are shown and explored. They were experimentally tested in more than 2 decades, from 0.03 to 5.8 nF, and controlled by single DC voltage from 0.1 to 1.0 V. The outputs of experimental measurements meet with the PSpice simulations and confirm the design validity.

Název v anglickém jazyce

Capacitance Multiplier Using Small Values of Multiplication Factors for Adjustability Extension and Parasitic Resistance Cancellation Technique

Popis výsledku anglicky

This paper presents a new concept of a capacitance multiplier using the topology of differential voltage buffer and current conveyor, where the capacitor is connected to the current input terminal. The presented topology overcomes the typical issue known from similar solutions, i.e. creation of an undesired lossy character of the impedance plot. The added feedback path in the structure serves for minimization of the serial parasitic resistance of the current input terminal as well as the output resistance of differential voltage buffer. The electronic driving of the current and voltage internal gains of the active elements allows the adjustment of the capacitance multiplication factor as well as readjustment of the overall capacitance structure between the lossy and lossless modes of operation. The adjustment of the multiplication factor intentionally targets low ranges of gains. Despite that the multiplication factor equals or is less than 1, the range of adjustability is very wide. Simple modifications of the proposed concept leading to the differential-mode operation and enhancement of the multiplication factor are shown and explored. They were experimentally tested in more than 2 decades, from 0.03 to 5.8 nF, and controlled by single DC voltage from 0.1 to 1.0 V. The outputs of experimental measurements meet with the PSpice simulations and confirm the design validity.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

<a href="/cs/project/GA19-22248S" target="_blank" >GA19-22248S: Deterministické, chaotické a stochastické jevy v sub-mikronových integrovaných strukturách</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2020

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

IEEE Access

ISSN

2169-3536

e-ISSN

—

Svazek periodika

8

Číslo periodika v rámci svazku

1

Stát vydavatele periodika

US - Spojené státy americké

Počet stran výsledku

11

Strana od-do

144382-144392

Kód UT WoS článku

000560362300001

EID výsledku v databázi Scopus

2-s2.0-85090269683