Instruction mapping techniques for processors with very long instruction word architectures

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F22%3APU146658" target="_blank" >RIV/00216305:26220/22:PU146658 - isvavai.cz</a>

Výsledek na webu

<a href="http://iris.elf.stuba.sk/JEEEC/data/pdf/6_122-03.pdf" target="_blank" >http://iris.elf.stuba.sk/JEEEC/data/pdf/6_122-03.pdf</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.2478/jee-2022-0053" target="_blank" >10.2478/jee-2022-0053</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Instruction mapping techniques for processors with very long instruction word architectures

Popis výsledku v původním jazyce

This paper presents an instruction mapping technique for generating a low-level assembly code for digital signal processing algorithms. This technique helps developers to implement retargetable kernel functions with the performance benefits of the low-level assembly languages. The approach is aimed at exceptionally long instruction word (VLIW) architectures, which benefits the most from the proposed method. Mapped algorithms are described by the signal-flow graphs, which are used to find possible parallel operations. The algorithm is converted into low-level code and mapped to the target architecture. This process also introduces the optimization of instruction mapping priority, which leads to the more effective code. The technique was verified on selected kernels, compared to the common programming methods, and proved that it is suitable for VLIW architectures and for portability to other systems.

Název v anglickém jazyce

Instruction mapping techniques for processors with very long instruction word architectures

Popis výsledku anglicky

This paper presents an instruction mapping technique for generating a low-level assembly code for digital signal processing algorithms. This technique helps developers to implement retargetable kernel functions with the performance benefits of the low-level assembly languages. The approach is aimed at exceptionally long instruction word (VLIW) architectures, which benefits the most from the proposed method. Mapped algorithms are described by the signal-flow graphs, which are used to find possible parallel operations. The algorithm is converted into low-level code and mapped to the target architecture. This process also introduces the optimization of instruction mapping priority, which leads to the more effective code. The technique was verified on selected kernels, compared to the common programming methods, and proved that it is suitable for VLIW architectures and for portability to other systems.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

—

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2022

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Journal of Electrical Engineering

ISSN

1335-3632

e-ISSN

1339-309X

Svazek periodika

73

Číslo periodika v rámci svazku

6

Stát vydavatele periodika

SK - Slovenská republika

Počet stran výsledku

9

Strana od-do

387-395

Kód UT WoS článku

000903573600003

EID výsledku v databázi Scopus

2-s2.0-85144973397