Implementation of a Multipath Fully Differential OTA in 0.18-mu m CMOS Process

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F22%3APU146817" target="_blank" >RIV/00216305:26220/22:PU146817 - isvavai.cz</a>

Nalezeny alternativní kódy

RIV/68407700:21460/23:00362546

Výsledek na webu

<a href="https://ieeexplore.ieee.org/document/9944072" target="_blank" >https://ieeexplore.ieee.org/document/9944072</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/TVLSI.2022.3218741" target="_blank" >10.1109/TVLSI.2022.3218741</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Implementation of a Multipath Fully Differential OTA in 0.18-mu m CMOS Process

Popis výsledku v původním jazyce

This brief implements a highly efficient fully differential transconductance amplifier, based on several input-to-output paths. Some traditional techniques, such as positive feedback, nonlinear tail current sources, and current mirror-based paths, are combined to increase the transconductance, thus leading to larger dc gain and higher gain bandwidth (GBW) product. Two flipped voltage-follower (FVF) cells are employed as variable current sources to provide class-AB operation and adaptive biasing of all other drivers. The proposed structure includes several input-to-output paths that play the role of dynamic current boosters during the slewing phase, thus improving the slew rate (SR) performance. The circuit was fabricated in a TSMC 0.18-mu m CMOS process with a silicon area of 54.5 x 30.1 mu m. Experimental results show a GBW of 173.3 MHz, a dc gain of 72.7 dB, and an SR of 139.4 V/mu s for a capacitive load of 2 x 5 pF. The proposed circuit consumes 619 mu W of power, under a supply voltage of 1.8 V.

Název v anglickém jazyce

Implementation of a Multipath Fully Differential OTA in 0.18-mu m CMOS Process

Popis výsledku anglicky

This brief implements a highly efficient fully differential transconductance amplifier, based on several input-to-output paths. Some traditional techniques, such as positive feedback, nonlinear tail current sources, and current mirror-based paths, are combined to increase the transconductance, thus leading to larger dc gain and higher gain bandwidth (GBW) product. Two flipped voltage-follower (FVF) cells are employed as variable current sources to provide class-AB operation and adaptive biasing of all other drivers. The proposed structure includes several input-to-output paths that play the role of dynamic current boosters during the slewing phase, thus improving the slew rate (SR) performance. The circuit was fabricated in a TSMC 0.18-mu m CMOS process with a silicon area of 54.5 x 30.1 mu m. Experimental results show a GBW of 173.3 MHz, a dc gain of 72.7 dB, and an SR of 139.4 V/mu s for a capacitive load of 2 x 5 pF. The proposed circuit consumes 619 mu W of power, under a supply voltage of 1.8 V.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

20200 - Electrical engineering, Electronic engineering, Information engineering

Projekt

—

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2022

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

ISSN

1063-8210

e-ISSN

1557-9999

Svazek periodika

31

Číslo periodika v rámci svazku

1

Stát vydavatele periodika

US - Spojené státy americké

Počet stran výsledku

5

Strana od-do

147-151

Kód UT WoS článku

000881953100001

EID výsledku v databázi Scopus

2-s2.0-85141614955