Design of Multi-bit Pulsed Latches with Scan Input in CMOS ONK65 Technology

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F23%3APU150810" target="_blank" >RIV/00216305:26220/23:PU150810 - isvavai.cz</a>

Výsledek na webu

<a href="https://www.radioeng.cz/fulltexts/2023/23_04_0557_0567.pdf" target="_blank" >https://www.radioeng.cz/fulltexts/2023/23_04_0557_0567.pdf</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.13164/re.2023.0557" target="_blank" >10.13164/re.2023.0557</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Design of Multi-bit Pulsed Latches with Scan Input in CMOS ONK65 Technology

Popis výsledku v původním jazyce

This paper presents a new multi-bit pulse latch design that places innovative emphasis on the integration of scan input for automatic test pattern generation (ATPG). Two different designs have been developed in ONK65 technology (65 nm process): the first with standard threshold voltage (SVT) tailored for consumer products and the second with high threshold voltage (HVT) for automotive, each addressing specific aspects of process, voltage, and temperature (PVT). Multi-bit pulse latches offer a more efficient alternative to multi-bit flip-flop circuits and promise significant power and area savings. However, the efficiency of these latches depends on the technology, library type and customer requirements. A multi-bit pulse latch consists of a pulse generator and a pulsed latch. Each component is carefully designed for its specific purpose and the most appropriate topology is selected. Furthermore, the paper serves as a comprehensive guide to the design of low-power digital cells. It rethinks the topology design approach by emphasizing the scan input and presents simulation results for both components of the multi-bit pulse latch, highlighting their advantages. The results show that a less strict PVT offers greater benefits than a strict PVT.

Název v anglickém jazyce

Design of Multi-bit Pulsed Latches with Scan Input in CMOS ONK65 Technology

Popis výsledku anglicky

This paper presents a new multi-bit pulse latch design that places innovative emphasis on the integration of scan input for automatic test pattern generation (ATPG). Two different designs have been developed in ONK65 technology (65 nm process): the first with standard threshold voltage (SVT) tailored for consumer products and the second with high threshold voltage (HVT) for automotive, each addressing specific aspects of process, voltage, and temperature (PVT). Multi-bit pulse latches offer a more efficient alternative to multi-bit flip-flop circuits and promise significant power and area savings. However, the efficiency of these latches depends on the technology, library type and customer requirements. A multi-bit pulse latch consists of a pulse generator and a pulsed latch. Each component is carefully designed for its specific purpose and the most appropriate topology is selected. Furthermore, the paper serves as a comprehensive guide to the design of low-power digital cells. It rethinks the topology design approach by emphasizing the scan input and presents simulation results for both components of the multi-bit pulse latch, highlighting their advantages. The results show that a less strict PVT offers greater benefits than a strict PVT.

Druh

J_SC - Článek v periodiku v databázi SCOPUS

CEP obor

—

OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

—

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2023

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Radioengineering

ISSN

1210-2512

e-ISSN

—

Svazek periodika

32

Číslo periodika v rámci svazku

4

Stát vydavatele periodika

CZ - Česká republika

Počet stran výsledku

11

Strana od-do

557-567

Kód UT WoS článku

—

EID výsledku v databázi Scopus

2-s2.0-85177688955