Influence and Algorithmic Suppression of Parasitic Capacitance of the R-C-NR Layer Contacts in Thick-Film Fractional-Order Capacitor

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F24%3APU151247" target="_blank" >RIV/00216305:26220/24:PU151247 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1109/SoutheastCon52093.2024.10500259" target="_blank" >http://dx.doi.org/10.1109/SoutheastCon52093.2024.10500259</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/SoutheastCon52093.2024.10500259" target="_blank" >10.1109/SoutheastCon52093.2024.10500259</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Influence and Algorithmic Suppression of Parasitic Capacitance of the R-C-NR Layer Contacts in Thick-Film Fractional-Order Capacitor

Popis výsledku v původním jazyce

The realization of capacitive fractional-order circuit elements based on distributed layer R-C-NR (resistive, capacitive, resistive) structures is analyzed for implementation in thick-film technology. The metal contacts for layer connections are found to introduce parasitic capacitance which is modeled in this work treating the contacts as lumped-element capacitors. A design method for the algorithmic suppression of the parasitic capacitance is presented. The design method uses a genetic algorithm to optimize the interconnections and parameters of the R-C-NR structures that comprise the circuit to counteract the effects of the parasitic capacitance. Using modified nodal analysis, the impact of the parasitic capacitance on the admittance characteristics is simulated and suppressed by the algorithm. Simulations validate this method, with best performance for fractional orders between 0 and 0.5, where it is possible to design circuits with a frequency range of constant admittance phase of 2.5 to 4 decades with a maximum admittance phase deviation of 2 degrees.

Název v anglickém jazyce

Influence and Algorithmic Suppression of Parasitic Capacitance of the R-C-NR Layer Contacts in Thick-Film Fractional-Order Capacitor

Popis výsledku anglicky

The realization of capacitive fractional-order circuit elements based on distributed layer R-C-NR (resistive, capacitive, resistive) structures is analyzed for implementation in thick-film technology. The metal contacts for layer connections are found to introduce parasitic capacitance which is modeled in this work treating the contacts as lumped-element capacitors. A design method for the algorithmic suppression of the parasitic capacitance is presented. The design method uses a genetic algorithm to optimize the interconnections and parameters of the R-C-NR structures that comprise the circuit to counteract the effects of the parasitic capacitance. Using modified nodal analysis, the impact of the parasitic capacitance on the admittance characteristics is simulated and suppressed by the algorithm. Simulations validate this method, with best performance for fractional orders between 0 and 0.5, where it is possible to design circuits with a frequency range of constant admittance phase of 2.5 to 4 decades with a maximum admittance phase deviation of 2 degrees.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

<a href="/cs/project/GA23-06070S" target="_blank" >GA23-06070S: Základní výzkum v návrhu CMOS prvků fraktálního řádu</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2024

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of IEEE SoutheastCon 2024 Conference

ISBN

979-8-3503-1710-7

ISSN

—

e-ISSN

—

Počet stran výsledku

8

Strana od-do

1235-1242

Název nakladatele

IEEE

Místo vydání

Atlanta, GA, USA

Místo konání akce

Atlanta, Georgia

Datum konání akce

15. 3. 2024

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

001219464000202