Representation of Datapath Structure in Predicate Logic and its Implementation in Prolog

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F03%3APU42561" target="_blank" >RIV/00216305:26230/03:PU42561 - isvavai.cz</a>

Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Representation of Datapath Structure in Predicate Logic and its Implementation in Prolog

Popis výsledku v původním jazyce

The goal of our research is to develop a methodology for a digital circuit testability analysis. It is reached through the analysis of data paths which exist in the circuit as result of the design process to utilize them for diagnostic data transfers, the i path concept is used. A formal approach allows create a formal model of a circuit, describe its diagnostic properties and describe testability analysis algorithms, all of them formally. Due to the fact that all objects in the datapath structure of thhe circuit and its properties from the testability analysis point of view are described in language of predicate logic, the Prolog language was chosen. It includes tools converting VHDL description of the circuit structure and its properties into facts and clauses which establish facts database. On base of such a database i path search algorithm is implemented.

Název v anglickém jazyce

Representation of Datapath Structure in Predicate Logic and its Implementation in Prolog

Popis výsledku anglicky

The goal of our research is to develop a methodology for a digital circuit testability analysis. It is reached through the analysis of data paths which exist in the circuit as result of the design process to utilize them for diagnostic data transfers, the i path concept is used. A formal approach allows create a formal model of a circuit, describe its diagnostic properties and describe testability analysis algorithms, all of them formally. Due to the fact that all objects in the datapath structure of thhe circuit and its properties from the testability analysis point of view are described in language of predicate logic, the Prolog language was chosen. It includes tools converting VHDL description of the circuit structure and its properties into facts and clauses which establish facts database. On base of such a database i path search algorithm is implemented.

Druh

D - Stať ve sborníku

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

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Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2003

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of International Carpathian Control Conference

ISBN

80-7099-509-2

ISSN

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e-ISSN

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Počet stran výsledku

4

Strana od-do

727-730

Název nakladatele

The University of Technology Košice

Místo vydání

Košice

Místo konání akce

Vysoké Tatry

Datum konání akce

26. 5. 2003

Typ akce podle státní příslušnosti

EUR - Evropská akce

Kód UT WoS článku

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