Identifikace registrů v RTL obvodech

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F04%3APU49270" target="_blank" >RIV/00216305:26230/04:PU49270 - isvavai.cz</a>

Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

The Identification of Registers in RTL Structures

Popis výsledku v původním jazyce

A highly efficient test schedule can be created for a given digital circuit if a proper test-scheduling algorithm is selected and if the circuit fulfils several criteria that affect the quality of a resulting test schedule significantly and independentlyon any scheduling algorithm. If a design for testability techniques are applied to the circuit structure, the way in which they are applied have a big impact on those circuit properties. Thus, it is feasible to deal with the relation between applicationn of selected design for testability techniques and the quality of a resulting test schedule in detail. This is a wide research area. Our paper deals with the register selection technique through which a test will be applied. The paper presents a methodology for selecting registers for the test application in such a way that the cardinality of a set of selected registers is minimized and test resources allocated to functional units are shared in a maximum way. Proposed methodology is mat

Název v anglickém jazyce

The Identification of Registers in RTL Structures

Popis výsledku anglicky

A highly efficient test schedule can be created for a given digital circuit if a proper test-scheduling algorithm is selected and if the circuit fulfils several criteria that affect the quality of a resulting test schedule significantly and independentlyon any scheduling algorithm. If a design for testability techniques are applied to the circuit structure, the way in which they are applied have a big impact on those circuit properties. Thus, it is feasible to deal with the relation between applicationn of selected design for testability techniques and the quality of a resulting test schedule in detail. This is a wide research area. Our paper deals with the register selection technique through which a test will be applied. The paper presents a methodology for selecting registers for the test application in such a way that the cardinality of a set of selected registers is minimized and test resources allocated to functional units are shared in a maximum way. Proposed methodology is mat

Druh

D - Stať ve sborníku

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

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Projekt

<a href="/cs/project/GA102%2F04%2F0737" target="_blank" >GA102/04/0737: Moderní metody syntézy číslicových systémů</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2004

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Preliminary Proceedings of 1st International Symposium on Leveraging Applications of Formal Methods ISOLA 2004

ISBN

3-540-41613

ISSN

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e-ISSN

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Počet stran výsledku

4

Strana od-do

317-320

Název nakladatele

Department of Computer Science of University of Cyprus

Místo vydání

Nicosia

Místo konání akce

Amathus hotel, Poseidon avenue, 8098 Paphos

Datum konání akce

1. 10. 2004

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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