Polymorfní hradla v návrhu a testování číslicových obvodů

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F08%3APU76687" target="_blank" >RIV/00216305:26230/08:PU76687 - isvavai.cz</a>

Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Polymorphic Gates in Design and Test of Digital Circuits

Popis výsledku v původním jazyce

Polymorphic gates are unconventional logic components which can switch their logic functions according to changing environment. The first part of this study presents an evolutionary approach to the design of polymorphic modules which exhibit different logic functions in different environments. The most complicated circuit that we evolved contains more than 100 gates. The second part of this study shows how to reduce the number of test vectors of a digital circuit by replacing some of its gates by polymorphic gates. In the first polymorphic mode, the circuit implements the original function. When switched to the second polymorphic mode, it can be tested using fewer test vectors than in the first polymorphic mode; however, the same fault coverage is obtained. The number of test vectors was reduced on 50-91% of its original volume for six benchmark circuits. The paper also discusses various obstacles which one has to deal with during a practical utilization of polymorphic gates. <br>

Název v anglickém jazyce

Polymorphic Gates in Design and Test of Digital Circuits

Popis výsledku anglicky

Polymorphic gates are unconventional logic components which can switch their logic functions according to changing environment. The first part of this study presents an evolutionary approach to the design of polymorphic modules which exhibit different logic functions in different environments. The most complicated circuit that we evolved contains more than 100 gates. The second part of this study shows how to reduce the number of test vectors of a digital circuit by replacing some of its gates by polymorphic gates. In the first polymorphic mode, the circuit implements the original function. When switched to the second polymorphic mode, it can be tested using fewer test vectors than in the first polymorphic mode; however, the same fault coverage is obtained. The number of test vectors was reduced on 50-91% of its original volume for six benchmark circuits. The paper also discusses various obstacles which one has to deal with during a practical utilization of polymorphic gates. <br>

Druh

J_x - Nezařazeno - Článek v odborném periodiku (Jimp, Jsc a Jost)

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

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Projekt

<a href="/cs/project/GA102%2F06%2F0599" target="_blank" >GA102/06/0599: Metody návrhu polymorfních číslicových obvodů</a><br>

Návaznosti

Z - Vyzkumny zamer (s odkazem do CEZ)

Rok uplatnění

2008

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

International Journal of Unconventional Computing

ISSN

1548-7199

e-ISSN

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Svazek periodika

4

Číslo periodika v rámci svazku

2

Stát vydavatele periodika

US - Spojené státy americké

Počet stran výsledku

18

Strana od-do

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Kód UT WoS článku

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EID výsledku v databázi Scopus

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