SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F11%3APU96032" target="_blank" >RIV/00216305:26230/11:PU96032 - isvavai.cz</a>

Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems

Popis výsledku v původním jazyce

In the paper, the SEU simulation framework for testing fault tolerant system designs implemented into FPGA is presented. The framework is based on SEU generation outside FPGA (in personal computer) and the transport of modified bitstream through the JTAGinterface and subsequent  dynamic reconfiguration of  FPGA.  It allows to select region of the FPGA for  SEU placing. The SEU simulator does not require any changes in the tested design and is fully independent on the function implemented into FPGA. Therequirements on the SEU generator and its properties are described in the paper as well. The external SEU generator for Xilinx FPGA was implemented and verified on evaluation board ML506 with Vitrex5 for different types of RTL circuits and fault tolerant architectures. The experimatal results demonstrated the effectiveness of the methodology.

Název v anglickém jazyce

SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems

Popis výsledku anglicky

In the paper, the SEU simulation framework for testing fault tolerant system designs implemented into FPGA is presented. The framework is based on SEU generation outside FPGA (in personal computer) and the transport of modified bitstream through the JTAGinterface and subsequent  dynamic reconfiguration of  FPGA.  It allows to select region of the FPGA for  SEU placing. The SEU simulator does not require any changes in the tested design and is fully independent on the function implemented into FPGA. Therequirements on the SEU generator and its properties are described in the paper as well. The external SEU generator for Xilinx FPGA was implemented and verified on evaluation board ML506 with Vitrex5 for different types of RTL circuits and fault tolerant architectures. The experimatal results demonstrated the effectiveness of the methodology.

Druh

D - Stať ve sborníku

CEP obor

IN - Informatika

OECD FORD obor

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Projekt

<a href="/cs/project/GA102%2F09%2F1668" target="_blank" >GA102/09/1668: Zvyšování spolehlivosti a provozuschopnosti v obvodech SoC</a><br>

Návaznosti

Z - Vyzkumny zamer (s odkazem do CEZ)

Rok uplatnění

2011

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

14th EUROMICRO Conference on Digital System Design

ISBN

978-0-7695-4494-6

ISSN

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e-ISSN

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Počet stran výsledku

8

Strana od-do

223-230

Název nakladatele

IEEE Computer Society

Místo vydání

Oulu

Místo konání akce

Oulu

Datum konání akce

31. 8. 2011

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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