Fault Tolerant System Design and SEU Injection based Testing

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F12%3APU98179" target="_blank" >RIV/00216305:26230/12:PU98179 - isvavai.cz</a>

Výsledek na webu

<a href="http://www.fit.vutbr.cz/research/pubs/all.php?id=9902" target="_blank" >http://www.fit.vutbr.cz/research/pubs/all.php?id=9902</a>

DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Fault Tolerant System Design and SEU Injection based Testing

Popis výsledku v původním jazyce

The methodology for design and testing of fault tolerant systems implemented into an FPGA platform with different types of diagnostic techniques is presented in this paper. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance features of the digital design implemented into SRAM-based FPGA. The methodology includes detection and localization of a faulty module in the system and its repair and bringing the system back to the state in which it operates correctly. The automatic repair process of a faulty module is implemented by a partial dynamic reconfiguration driven by a generic controller inside FPGA. The presented methodology was verified on the ML506 development board with Virtex5 FPGA for different types of RTL components. Fault tolerant systems developed by the presented methodology were tested by means of the newly developed SEU simulation framework. The framework is based on the SEU simulation through the JTAG interface and allows us to select the region of the FPGA where the SEU is placed. The simulator does not require any changes in the tested design and is fully independent of the functions in the FPGA. The external SEU generator into FPGA is implemented and its function is verified on an evaluation board ML506 for several types of fault tolerant architectures. The experimental results show the fault coverage and SEU occurrence causing faulty behavior of verified architectures.

Název v anglickém jazyce

Fault Tolerant System Design and SEU Injection based Testing

Popis výsledku anglicky

The methodology for design and testing of fault tolerant systems implemented into an FPGA platform with different types of diagnostic techniques is presented in this paper. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance features of the digital design implemented into SRAM-based FPGA. The methodology includes detection and localization of a faulty module in the system and its repair and bringing the system back to the state in which it operates correctly. The automatic repair process of a faulty module is implemented by a partial dynamic reconfiguration driven by a generic controller inside FPGA. The presented methodology was verified on the ML506 development board with Virtex5 FPGA for different types of RTL components. Fault tolerant systems developed by the presented methodology were tested by means of the newly developed SEU simulation framework. The framework is based on the SEU simulation through the JTAG interface and allows us to select the region of the FPGA where the SEU is placed. The simulator does not require any changes in the tested design and is fully independent of the functions in the FPGA. The external SEU generator into FPGA is implemented and its function is verified on an evaluation board ML506 for several types of fault tolerant architectures. The experimental results show the fault coverage and SEU occurrence causing faulty behavior of verified architectures.

Druh

J_ost - Ostatní články v recenzovaných periodicích

CEP obor

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OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2013

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Microprocessors and Microsystems

ISSN

0141-9331

e-ISSN

1872-9436

Svazek periodika

2013

Číslo periodika v rámci svazku

37

Stát vydavatele periodika

NL - Nizozemsko

Počet stran výsledku

18

Strana od-do

155-173

Kód UT WoS článku

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EID výsledku v databázi Scopus

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