On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F11%3APU96050" target="_blank" >RIV/00216305:26230/11:PU96050 - isvavai.cz</a>

Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits

Popis výsledku v původním jazyce

Major drawback of high level design methodologies such as RTL can be seen in the following facts. First, they lack of sufficiently precise fault models - compared to sophisticated models available for low level description levels such as logic gate level. Second, since the structure of a design changes significantly with every logic synthesis run, testability analysis is typically performed only after final logic synthesis. As a consequence, results of the analysis could be obtained when it is very costly to reflect them in the high level design. The drawbacks can be removed in several ways. In the contribution, it is supposed the analysis is performed at RTL and is efficient enough to be run after each change in RTL design - giving a designer an immediate information about the change impact to testability parameters. Under the assumption, following requirements are posed to the analysis: low computational complexity and accuracy. The latter requirement is met if strong correlation is

Název v anglickém jazyce

On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits

Popis výsledku anglicky

Major drawback of high level design methodologies such as RTL can be seen in the following facts. First, they lack of sufficiently precise fault models - compared to sophisticated models available for low level description levels such as logic gate level. Second, since the structure of a design changes significantly with every logic synthesis run, testability analysis is typically performed only after final logic synthesis. As a consequence, results of the analysis could be obtained when it is very costly to reflect them in the high level design. The drawbacks can be removed in several ways. In the contribution, it is supposed the analysis is performed at RTL and is efficient enough to be run after each change in RTL design - giving a designer an immediate information about the change impact to testability parameters. Under the assumption, following requirements are posed to the analysis: low computational complexity and accuracy. The latter requirement is met if strong correlation is

Druh

D - Stať ve sborníku

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

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Projekt

<a href="/cs/project/GA102%2F09%2F1668" target="_blank" >GA102/09/1668: Zvyšování spolehlivosti a provozuschopnosti v obvodech SoC</a><br>

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2011

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the 14th Euromicro Conference on Digital System Design - Architectures, Methods and Tools 2011

ISBN

978-0-7695-4494-6

ISSN

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e-ISSN

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Počet stran výsledku

8

Strana od-do

367-374

Název nakladatele

IEEE Computer Society

Místo vydání

Oulu

Místo konání akce

Oulu

Datum konání akce

31. 8. 2011

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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