Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F11%3APU96104" target="_blank" >RIV/00216305:26230/11:PU96104 - isvavai.cz</a>

Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support

Popis výsledku v původním jazyce

This paper addresses the modelling and validation of an evolvable hardware architecture which can be mapped on a 2D systolic structure implemented on commercial reconfigurable FPGAs. The adaptation capabilities of the architecture are exercised to validate its evolvability. The underlying proposal is the use of a library of reconfigurable components characterised by their partial bitstreams, which are used by the Evolutionary Algorithm to find a solution to a given task. Evolution of image noise filtersis selected as the proof of concept application. Results show that computation speed of the resulting evolved circuit is higher than with the Virtual Reconfigurable Circuits approach, and this can be exploited on the evolution process by using dynamic reconfiguration.

Název v anglickém jazyce

Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support

Popis výsledku anglicky

This paper addresses the modelling and validation of an evolvable hardware architecture which can be mapped on a 2D systolic structure implemented on commercial reconfigurable FPGAs. The adaptation capabilities of the architecture are exercised to validate its evolvability. The underlying proposal is the use of a library of reconfigurable components characterised by their partial bitstreams, which are used by the Evolutionary Algorithm to find a solution to a given task. Evolution of image noise filtersis selected as the proof of concept application. Results show that computation speed of the resulting evolved circuit is higher than with the Virtual Reconfigurable Circuits approach, and this can be exploited on the evolution process by using dynamic reconfiguration.

Druh

D - Stať ve sborníku

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

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Projekt

<a href="/cs/project/GAP103%2F10%2F1517" target="_blank" >GAP103/10/1517: Natural computing na nekonvenčních platformách</a><br>

Návaznosti

Z - Vyzkumny zamer (s odkazem do CEZ)

Rok uplatnění

2011

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems

ISBN

978-1-4577-0599-1

ISSN

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e-ISSN

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Počet stran výsledku

8

Strana od-do

184-191

Název nakladatele

IEEE Computer Society

Místo vydání

Los Alamitos

Místo konání akce

San Diego

Datum konání akce

6. 6. 2011

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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