Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F15%3APU116923" target="_blank" >RIV/00216305:26230/15:PU116923 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1145/2700414" target="_blank" >http://dx.doi.org/10.1145/2700414</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1145/2700414" target="_blank" >10.1145/2700414</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware

Popis výsledku v původním jazyce

Field programmable gate arrays can be considered to be the most popular and successful platform for evolvable hardware. They allow to establish and later reconfigure candidate solutions. Recent work in the field of evolvable hardware includes the use of virtual and native reconfigurations. Both of these approaches have their disadvantages. The virtual reconfiguration is characterized by lower maximal operational frequency of the resulting solutions, and the native reconfiguration is slower. In this work, a hybrid approach is used merging the advantages while limiting the disadvantages of the virtual and native reconfigurations. The main contribution is the new low-level architecture for evolvable hardware in the new Zynq-7000 all programmable system-on-chip. The proposed architecture offers high flexibility by considering direct modification of the reconfigurable resources. The impact of the higher reconfiguration time of the native approach is limited by the dense placement of the proposed reconfigurable processing elements. These processing elements also ensure fast candidate evaluation. The proposed architecture is evaluated by evolutionary design of switching image filters. The experimental results demonstrate superiority over the previous approaches considering the time required for evolution, area overhead, and flexibility.

Název v anglickém jazyce

Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware

Popis výsledku anglicky

Field programmable gate arrays can be considered to be the most popular and successful platform for evolvable hardware. They allow to establish and later reconfigure candidate solutions. Recent work in the field of evolvable hardware includes the use of virtual and native reconfigurations. Both of these approaches have their disadvantages. The virtual reconfiguration is characterized by lower maximal operational frequency of the resulting solutions, and the native reconfiguration is slower. In this work, a hybrid approach is used merging the advantages while limiting the disadvantages of the virtual and native reconfigurations. The main contribution is the new low-level architecture for evolvable hardware in the new Zynq-7000 all programmable system-on-chip. The proposed architecture offers high flexibility by considering direct modification of the reconfigurable resources. The impact of the higher reconfiguration time of the native approach is limited by the dense placement of the proposed reconfigurable processing elements. These processing elements also ensure fast candidate evaluation. The proposed architecture is evaluated by evolutionary design of switching image filters. The experimental results demonstrate superiority over the previous approaches considering the time required for evolution, area overhead, and flexibility.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2015

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

ACM Transactions on Reconfigurable Technology and Systems

ISSN

1936-7406

e-ISSN

1936-7414

Svazek periodika

8

Číslo periodika v rámci svazku

3

Stát vydavatele periodika

US - Spojené státy americké

Počet stran výsledku

24

Strana od-do

1-24

Kód UT WoS článku

000355669800007

EID výsledku v databázi Scopus

2-s2.0-84930672639