Reflecting RTOS Model During WCET Timing Analysis: MSP430/FreeRTOS Case Study

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F12%3APU103010" target="_blank" >RIV/00216305:26230/12:PU103010 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.2478/v10198-012-0041-3" target="_blank" >http://dx.doi.org/10.2478/v10198-012-0041-3</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.2478/v10198-012-0041-3" target="_blank" >10.2478/v10198-012-0041-3</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Reflecting RTOS Model During WCET Timing Analysis: MSP430/FreeRTOS Case Study

Popis výsledku v původním jazyce

The determination of the execution time upper bound, commonly called Worst-Case Execution Time (WCET), is a necessary step in the development and validation process for real-time systems. The WCET analysis techniques can be classified as static or dynamic. While a high-level language code suffices for the static techniques, for a precise WCET analysis a target architecture or its authentic simulator able to run the final machine-level code of an analyzed application is needed by the dynamic techniques.In the paper, we have decided not only to present a novel hybrid timing analysis technique, but also to show its practical applicability in the area of WCET analysis over particular embedded architecture (MSP430) and real-time operating system (FreeRTOS). Novelty of the presented method can be seen in the fact the operating system model is reflected during the analysis in order to facilitate the process of derivating schedulability test formulas, create detail task/stack analysis etc. Ap

Název v anglickém jazyce

Reflecting RTOS Model During WCET Timing Analysis: MSP430/FreeRTOS Case Study

Popis výsledku anglicky

The determination of the execution time upper bound, commonly called Worst-Case Execution Time (WCET), is a necessary step in the development and validation process for real-time systems. The WCET analysis techniques can be classified as static or dynamic. While a high-level language code suffices for the static techniques, for a precise WCET analysis a target architecture or its authentic simulator able to run the final machine-level code of an analyzed application is needed by the dynamic techniques.In the paper, we have decided not only to present a novel hybrid timing analysis technique, but also to show its practical applicability in the area of WCET analysis over particular embedded architecture (MSP430) and real-time operating system (FreeRTOS). Novelty of the presented method can be seen in the fact the operating system model is reflected during the analysis in order to facilitate the process of derivating schedulability test formulas, create detail task/stack analysis etc. Ap

Druh

J_x - Nezařazeno - Článek v odborném periodiku (Jimp, Jsc a Jost)

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

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Projekt

<a href="/cs/project/ED1.1.00%2F02.0070" target="_blank" >ED1.1.00/02.0070: Centrum excelence IT4Innovations</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2012

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Acta Electrotechnica et Informatica

ISSN

1335-8243

e-ISSN

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Svazek periodika

12

Číslo periodika v rámci svazku

4

Stát vydavatele periodika

SK - Slovenská republika

Počet stran výsledku

13

Strana od-do

17-29

Kód UT WoS článku

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EID výsledku v databázi Scopus

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