T-CREST: Time-predictable Multi-Core Architecture for Embedded Systems

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F15%3A00229475" target="_blank" >RIV/68407700:21230/15:00229475 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1016/j.sysarc.2015.04.002" target="_blank" >http://dx.doi.org/10.1016/j.sysarc.2015.04.002</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1016/j.sysarc.2015.04.002" target="_blank" >10.1016/j.sysarc.2015.04.002</a>

Jazyk výsledku

angličtina

Název v původním jazyce

T-CREST: Time-predictable Multi-Core Architecture for Embedded Systems

Popis výsledku v původním jazyce

Real-time systems need time-predictable platforms to allow static analysis of the worst-case execution time (WCET). Standard multi-core processors are optimized for the average case and are hardly analyzable. Within the T-CREST project we propose novel solutions for time-predictable multi-core architectures that are optimized for the WCET instead of the average-case execution time. The resulting time-predictable resources (processors, interconnect, memory arbiter, and memory controller) and tools (compiler, WCET analysis) are designed to ease WCET analysis and to optimize WCET performance. Compared to other processors the WCET performance is outstanding. The T-CREST platform is evaluated with two industrial use cases. An application from the avionic domain demonstrates that tasks executing on different cores do not interfere with respect to their WCET. A signal processing application from the railway domain shows that the WCET can be reduced for computation-intensive tasks when distrib

Název v anglickém jazyce

T-CREST: Time-predictable Multi-Core Architecture for Embedded Systems

Popis výsledku anglicky

Real-time systems need time-predictable platforms to allow static analysis of the worst-case execution time (WCET). Standard multi-core processors are optimized for the average case and are hardly analyzable. Within the T-CREST project we propose novel solutions for time-predictable multi-core architectures that are optimized for the WCET instead of the average-case execution time. The resulting time-predictable resources (processors, interconnect, memory arbiter, and memory controller) and tools (compiler, WCET analysis) are designed to ease WCET analysis and to optimize WCET performance. Compared to other processors the WCET performance is outstanding. The T-CREST platform is evaluated with two industrial use cases. An application from the avionic domain demonstrates that tasks executing on different cores do not interfere with respect to their WCET. A signal processing application from the railway domain shows that the WCET can be reduced for computation-intensive tasks when distrib

Druh

J_x - Nezařazeno - Článek v odborném periodiku (Jimp, Jsc a Jost)

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

—

Projekt

—

Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2015

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Journal of Systems Architecture

ISSN

1383-7621

e-ISSN

—

Svazek periodika

61

Číslo periodika v rámci svazku

9

Stát vydavatele periodika

NL - Nizozemsko

Počet stran výsledku

23

Strana od-do

449-471

Kód UT WoS článku

000364271900006

EID výsledku v databázi Scopus

2-s2.0-84938494470