Hardware Architecture for the Fast Pattern Matching

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F13%3APU106307" target="_blank" >RIV/00216305:26230/13:PU106307 - isvavai.cz</a>

Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Hardware Architecture for the Fast Pattern Matching

Popis výsledku v původním jazyce

As the speed of current computer networks in- creases, it is necessary to protect networks by security systems such as firewalls and Intrusion Detection Systems (IDS) operating at multigigabit speeds. As attacks on modern networks became more and more complex, it is necessity to detect attack placed not only in single packet but at the level of network flows. Pattern matching in the network flows is the time-critical operation of many modern IDS. Most of the regularly used patterns are described by the regular expression. This work describes advanced hardware architecture for the fast regular expression matching based on the perfect hashing. The proposed architecture is scalable and can achieve multigigabit throughput per network flow.

Název v anglickém jazyce

Hardware Architecture for the Fast Pattern Matching

Popis výsledku anglicky

As the speed of current computer networks in- creases, it is necessary to protect networks by security systems such as firewalls and Intrusion Detection Systems (IDS) operating at multigigabit speeds. As attacks on modern networks became more and more complex, it is necessity to detect attack placed not only in single packet but at the level of network flows. Pattern matching in the network flows is the time-critical operation of many modern IDS. Most of the regularly used patterns are described by the regular expression. This work describes advanced hardware architecture for the fast regular expression matching based on the perfect hashing. The proposed architecture is scalable and can achieve multigigabit throughput per network flow.

Druh

D - Stať ve sborníku

CEP obor

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OECD FORD obor

20206 - Computer hardware and architecture

Projekt

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Návaznosti

Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2013

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

ISBN

978-1-4673-6133-0

ISSN

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e-ISSN

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Počet stran výsledku

4

Strana od-do

120-123

Název nakladatele

IEEE Computer Society

Místo vydání

Brno

Místo konání akce

Karlovy Vary

Datum konání akce

8. 4. 2013

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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