FPGA Prototyping and Accelerated Verification of ASIPs

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F15%3APU116997" target="_blank" >RIV/00216305:26230/15:PU116997 - isvavai.cz</a>

Výsledek na webu

<a href="https://www.fit.vut.cz/research/publication/10881/" target="_blank" >https://www.fit.vut.cz/research/publication/10881/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DDECS.2015.33" target="_blank" >10.1109/DDECS.2015.33</a>

Jazyk výsledku

angličtina

Název v původním jazyce

FPGA Prototyping and Accelerated Verification of ASIPs

Popis výsledku v původním jazyce

In current SoC verification, the trend is to create verification solutions that are tailored to specific issues in SoC or to specific architectures. The reason is that the complexity of these systems makes it difficult to use general verification approaches such as formal or simulation-based verification. This paper presents a solution that is targeted to one particular area - Application-Specific Instruction-Set Processors (ASIP) and multi-processor systems containing several ASIPs. We propose automated FPGA prototyping and accelerated verification of these systems while the accelerated verification environment corresponds to the principles of UVM (Universal Verification Methodology) therefore can easily be integrated. Automated generation of verification environments and acceleration of verification runnning on a real hardware platform makes this solution very unique and beneficial, not only in speed, but also in debugging specific hardware issues.

Název v anglickém jazyce

FPGA Prototyping and Accelerated Verification of ASIPs

Popis výsledku anglicky

In current SoC verification, the trend is to create verification solutions that are tailored to specific issues in SoC or to specific architectures. The reason is that the complexity of these systems makes it difficult to use general verification approaches such as formal or simulation-based verification. This paper presents a solution that is targeted to one particular area - Application-Specific Instruction-Set Processors (ASIP) and multi-processor systems containing several ASIPs. We propose automated FPGA prototyping and accelerated verification of these systems while the accelerated verification environment corresponds to the principles of UVM (Universal Verification Methodology) therefore can easily be integrated. Automated generation of verification environments and acceleration of verification runnning on a real hardware platform makes this solution very unique and beneficial, not only in speed, but also in debugging specific hardware issues.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2015

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems

ISBN

978-1-4799-6780-3

ISSN

—

e-ISSN

—

Počet stran výsledku

4

Strana od-do

145-148

Název nakladatele

IEEE Computer Society

Místo vydání

Belgrade

Místo konání akce

Belgrade

Datum konání akce

22. 4. 2015

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

—