Automated Functional Verification of Application Specific Instruction-set Processors

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F13%3APU106324" target="_blank" >RIV/00216305:26230/13:PU106324 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1007/978-3-642-38853-8" target="_blank" >http://dx.doi.org/10.1007/978-3-642-38853-8</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1007/978-3-642-38853-8" target="_blank" >10.1007/978-3-642-38853-8</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Automated Functional Verification of Application Specific Instruction-set Processors

Popis výsledku v původním jazyce

Today's highly competitive market of consumer electronics is very sensitive to the time it takes to introduce a new product. However, the ever-growing complexity of application specific instruction-set processors (ASIPs) which are inseparable parts of nowadays complex embedded systems makes this task even more challenging as it is necessary to test and verify significantly bigger portion of logic, tricky timing behaviour or specific corner cases in a defined time schedule. As a consequence, the gap between the proposed verification plan and quality of verification tasks is widening due to this time restriction. One way how to solve this issue is using faster, efficient and cost-effective methods of verification. The aim of this paper is to introduce an automated generation of SystemVerilog verification environments (testbenches) for verification of ASIPs. Results show that our approach reduces the time and effort needed for implementation of testbenches significantly and furthermore, it improves the quality of verification itself.

Název v anglickém jazyce

Automated Functional Verification of Application Specific Instruction-set Processors

Popis výsledku anglicky

Today's highly competitive market of consumer electronics is very sensitive to the time it takes to introduce a new product. However, the ever-growing complexity of application specific instruction-set processors (ASIPs) which are inseparable parts of nowadays complex embedded systems makes this task even more challenging as it is necessary to test and verify significantly bigger portion of logic, tricky timing behaviour or specific corner cases in a defined time schedule. As a consequence, the gap between the proposed verification plan and quality of verification tasks is widening due to this time restriction. One way how to solve this issue is using faster, efficient and cost-effective methods of verification. The aim of this paper is to introduce an automated generation of SystemVerilog verification environments (testbenches) for verification of ASIPs. Results show that our approach reduces the time and effort needed for implementation of testbenches significantly and furthermore, it improves the quality of verification itself.

Druh

J_ost - Ostatní články v recenzovaných periodicích

CEP obor

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OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2013

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Environmental Software Systems

ISSN

1868-4238

e-ISSN

1868-422X

Svazek periodika

4

Číslo periodika v rámci svazku

403

Stát vydavatele periodika

DE - Spolková republika Německo

Počet stran výsledku

10

Strana od-do

128-138

Kód UT WoS článku

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EID výsledku v databázi Scopus

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