Regression Test Suites Optimization for Application-specific Instruction-set Processors and Their Use for Dependability Analysis
Identifikátory výsledku
Kód výsledku v IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F16%3APU121628" target="_blank" >RIV/00216305:26230/16:PU121628 - isvavai.cz</a>
Výsledek na webu
<a href="http://dx.doi.org/10.1109/DSD.2016.50" target="_blank" >http://dx.doi.org/10.1109/DSD.2016.50</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DSD.2016.50" target="_blank" >10.1109/DSD.2016.50</a>
Alternativní jazyky
Jazyk výsledku
angličtina
Název v původním jazyce
Regression Test Suites Optimization for Application-specific Instruction-set Processors and Their Use for Dependability Analysis
Popis výsledku v původním jazyce
Nowadays, Application-specific Instruction-set Processors (ASIPs) are an important part of embedded systems, especially those which are utilized in Internet of Things (IoT). They can be optimized for high performance, small area or low power consumption by changes in their instruction set or by various changes in their hardware architecture. With fast prototyping of ASIPs, another very important issue arises. It is fast verification of such changes, ideally with optimized test suites, so comprehensive and long-running verification after every change can be avoided. In this paper, a new technique for building optimized regression suites for ASIPs is proposed which is based on the genetic algorithm. Experiments show that using this technique, reduction of the original test suite from first phase verification is significant, the new optimized regression suite remains strong in checking key functionality of an ASIP and a considerable improvement in the verification runtime can be achieved. Moreover, the paper shows a proposal of multi-domain application of the regression suites in evaluating dependability of FPGA-based ASIP prototypes.
Název v anglickém jazyce
Regression Test Suites Optimization for Application-specific Instruction-set Processors and Their Use for Dependability Analysis
Popis výsledku anglicky
Nowadays, Application-specific Instruction-set Processors (ASIPs) are an important part of embedded systems, especially those which are utilized in Internet of Things (IoT). They can be optimized for high performance, small area or low power consumption by changes in their instruction set or by various changes in their hardware architecture. With fast prototyping of ASIPs, another very important issue arises. It is fast verification of such changes, ideally with optimized test suites, so comprehensive and long-running verification after every change can be avoided. In this paper, a new technique for building optimized regression suites for ASIPs is proposed which is based on the genetic algorithm. Experiments show that using this technique, reduction of the original test suite from first phase verification is significant, the new optimized regression suite remains strong in checking key functionality of an ASIP and a considerable improvement in the verification runtime can be achieved. Moreover, the paper shows a proposal of multi-domain application of the regression suites in evaluating dependability of FPGA-based ASIP prototypes.
Klasifikace
Druh
D - Stať ve sborníku
CEP obor
—
OECD FORD obor
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Návaznosti výsledku
Projekt
<a href="/cs/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>
Návaznosti
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach
Ostatní
Rok uplatnění
2016
Kód důvěrnosti údajů
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Údaje specifické pro druh výsledku
Název statě ve sborníku
Proceedings of the 19th Euromicro Conference on Digital Systems Design
ISBN
978-1-5090-2816-0
ISSN
—
e-ISSN
—
Počet stran výsledku
8
Strana od-do
380-387
Název nakladatele
IEEE Computer Society
Místo vydání
Limassol Cyprus
Místo konání akce
Limassol
Datum konání akce
31. 8. 2016
Typ akce podle státní příslušnosti
WRD - Celosvětová akce
Kód UT WoS článku
000386638800050