Dynamically Reconfigurable Architecture with Atomic Configuration Updates for Flexible Regular Expressions Matching in FPGA

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F16%3APU121630" target="_blank" >RIV/00216305:26230/16:PU121630 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1109/DSD.2016.109" target="_blank" >http://dx.doi.org/10.1109/DSD.2016.109</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DSD.2016.109" target="_blank" >10.1109/DSD.2016.109</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Dynamically Reconfigurable Architecture with Atomic Configuration Updates for Flexible Regular Expressions Matching in FPGA

Popis výsledku v původním jazyce

Regular expressions matching is commonly used in network security devices in order to detect malicious network traffic. The security device must be able to update set of used regular expressions as soon as possible. The update operation must not disrupt normal operations of the security device. Therefore, the update must be done atomically. Current reconfigurable architectures are not suitable for highly integrated embedded network security devices because they require either additional external FPGA memory, external ASICs or require partial reconfiguration of the FPGA. Also, architectures based on deterministic finite automaton suffers from significant time complexity even for real-word sets of regular expressions. Therefore, in this paper we introduce reconfigurable architecture with atomic updates suitable for real-world sets of regular expressions. We take inspiration from previous designs for both ASICs and FPGAs and propose regular expressions matching architecture with significantly lower consumption of FPGA resources than previous reconfigurable FPGA design. The proposed architecture uses an interconnection matrix with a linear space complexity, while the previous one uses an interconnection matrix with a quadratic space complexity. The proposed architecture consumes from 6,9 to 48.9 times less LUTs than previous dynamically reconfigurable FPGA design. Single matched symbol utilizes between 4,35 and 32,2 LUTs.

Název v anglickém jazyce

Dynamically Reconfigurable Architecture with Atomic Configuration Updates for Flexible Regular Expressions Matching in FPGA

Popis výsledku anglicky

Regular expressions matching is commonly used in network security devices in order to detect malicious network traffic. The security device must be able to update set of used regular expressions as soon as possible. The update operation must not disrupt normal operations of the security device. Therefore, the update must be done atomically. Current reconfigurable architectures are not suitable for highly integrated embedded network security devices because they require either additional external FPGA memory, external ASICs or require partial reconfiguration of the FPGA. Also, architectures based on deterministic finite automaton suffers from significant time complexity even for real-word sets of regular expressions. Therefore, in this paper we introduce reconfigurable architecture with atomic updates suitable for real-world sets of regular expressions. We take inspiration from previous designs for both ASICs and FPGAs and propose regular expressions matching architecture with significantly lower consumption of FPGA resources than previous reconfigurable FPGA design. The proposed architecture uses an interconnection matrix with a linear space complexity, while the previous one uses an interconnection matrix with a quadratic space complexity. The proposed architecture consumes from 6,9 to 48.9 times less LUTs than previous dynamically reconfigurable FPGA design. Single matched symbol utilizes between 4,35 and 32,2 LUTs.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

<a href="/cs/project/VI20152019001" target="_blank" >VI20152019001: Sondy pro analýzu a filtraci provozu na úrovni aplikačních protokolů</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2016

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of The 19th Euromicro Conference on Digital Systems Design

ISBN

978-1-5090-2816-0

ISSN

—

e-ISSN

—

Počet stran výsledku

8

Strana od-do

591-598

Název nakladatele

IEEE Computer Society

Místo vydání

Limassol

Místo konání akce

Limassol

Datum konání akce

31. 8. 2016

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000386638800077