High Performance Computing on Low Power Devices

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F16%3APU121651" target="_blank" >RIV/00216305:26230/16:PU121651 - isvavai.cz</a>

Výsledek na webu

<a href="http://www.fit.vutbr.cz/events/pad2016/download/sbornik_pad_2016.pdf" target="_blank" >http://www.fit.vutbr.cz/events/pad2016/download/sbornik_pad_2016.pdf</a>

DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

High Performance Computing on Low Power Devices

Popis výsledku v původním jazyce

Nowadays, the power efficiency of modern processors is becoming more and more important next to the overall performance itself. Many programming tasks and problems do not scale very well with higher number of cores due to being memory or communication bound, therefore it is often not beneficial to use faster chips to achieve better runtimes. In this case, employing slower low power processors or accelerators may be much more efficient, mainly because it is possible to get the same results using much less energy. Dynamic runtime adjustments applied to the system based on the properties of a given algorithm, such as frequency and voltage scaling or switching off unneeded parts, may further enhance power efficiency. This paper describes the benefits of using low power chips for building an HPC cluster, the group of algorithms where this approach can be useful, possible system adjustments towards better power efficiency, results achieved so far and future plans.

Název v anglickém jazyce

High Performance Computing on Low Power Devices

Popis výsledku anglicky

Nowadays, the power efficiency of modern processors is becoming more and more important next to the overall performance itself. Many programming tasks and problems do not scale very well with higher number of cores due to being memory or communication bound, therefore it is often not beneficial to use faster chips to achieve better runtimes. In this case, employing slower low power processors or accelerators may be much more efficient, mainly because it is possible to get the same results using much less energy. Dynamic runtime adjustments applied to the system based on the properties of a given algorithm, such as frequency and voltage scaling or switching off unneeded parts, may further enhance power efficiency. This paper describes the benefits of using low power chips for building an HPC cluster, the group of algorithms where this approach can be useful, possible system adjustments towards better power efficiency, results achieved so far and future plans.

Druh

D - Stať ve sborníku

CEP obor

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OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

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Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2016

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Computer achitectures and diagnostics 2016

ISBN

978-80-214-5376-0

ISSN

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e-ISSN

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Počet stran výsledku

4

Strana od-do

81-84

Název nakladatele

Faculty of Information Technology BUT

Místo vydání

Brno

Místo konání akce

Bořetice

Datum konání akce

14. 9. 2016

Typ akce podle státní příslušnosti

CST - Celostátní akce

Kód UT WoS článku

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