Evolutionary design of hash function pairs for network filters

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F17%3APU123167" target="_blank" >RIV/00216305:26230/17:PU123167 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1016/j.asoc.2017.03.009" target="_blank" >http://dx.doi.org/10.1016/j.asoc.2017.03.009</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1016/j.asoc.2017.03.009" target="_blank" >10.1016/j.asoc.2017.03.009</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Evolutionary design of hash function pairs for network filters

Popis výsledku v původním jazyce

Network filtering is a challenging area in high-speed computer networks, mostly because lots of filtering rules are required and there is only a limited time available for matching these rules. Therefore, network filters accelerated by field-programmable gate arrays (FPGAs) are becoming common where the fast lookup of filtering rules is achieved by the use of hash tables. It is desirable to be able to fill-up these tables efficiently, i.e. to achieve a high table-load factor in order to reduce the offline time of the network filter due to rehashing and/or table replacement. A parallel reconfigurable hash function tuned by an evolutionary algorithm (EA) is proposed in this paper for Internet Protocol (IP) address filtering in FPGAs. The EA fine-tunes the reconfigurable hash function for a given set of IP addresses. The experiments demonstrate that the proposed hash function provides high-speed lookup and achieves a higher table-load factor in comparison with conventional solutions.

Název v anglickém jazyce

Evolutionary design of hash function pairs for network filters

Popis výsledku anglicky

Network filtering is a challenging area in high-speed computer networks, mostly because lots of filtering rules are required and there is only a limited time available for matching these rules. Therefore, network filters accelerated by field-programmable gate arrays (FPGAs) are becoming common where the fast lookup of filtering rules is achieved by the use of hash tables. It is desirable to be able to fill-up these tables efficiently, i.e. to achieve a high table-load factor in order to reduce the offline time of the network filter due to rehashing and/or table replacement. A parallel reconfigurable hash function tuned by an evolutionary algorithm (EA) is proposed in this paper for Internet Protocol (IP) address filtering in FPGAs. The EA fine-tunes the reconfigurable hash function for a given set of IP addresses. The experiments demonstrate that the proposed hash function provides high-speed lookup and achieves a higher table-load factor in comparison with conventional solutions.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

<a href="/cs/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2017

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

APPLIED SOFT COMPUTING

ISSN

1568-4946

e-ISSN

1872-9681

Svazek periodika

56

Číslo periodika v rámci svazku

7

Stát vydavatele periodika

NL - Nizozemsko

Počet stran výsledku

9

Strana od-do

173-181

Kód UT WoS článku

000402364000014

EID výsledku v databázi Scopus

2-s2.0-85029600112